6/4/2004 - Real Intent Inc. of Santa Clara, California, the leading supplier of Formal Assertion-Based Verification (ABV) software for Block-to-Chip level electronic system design, announced that its flagship product VerixTM version 4.3 is now shipping with support for PSL - Accellera's Property Specification Language.
PSL is a powerful, concise language for assertion specification and functional modeling. As an interoperable specification language, it allows designers to use the same assertions to drive both simulation and formal verification methodologies while using tools from multiple vendors.
"The growing acceptance and demand for PSL, Accellera's new verification standard, has been a catalyst for our business," remarked Dr. Prakash Narain, Real Intent's President and CEO. "With this release of PSL support in Verix, we allow designers to apply the power of formal analysis in their flow and leverage standards that protect their investments and improve their verification ROI."
"We are pleased that the PSL standard, based on the Sugar language from IBM, is receiving support from numerous EDA companies," remarked Dr. Yaron Wolfsthal, Sr. Mgr., Advanced Verification Technologies, IBM Haifa Research Lab, where Sugar was conceived. "By supporting PSL, these companies are improving the way designers do their job by enabling them to capture design intent using PSL assertions and verify them in both simulation and formal verification tools. This trend, with the recent addition of Real Intent's support for PSL, gives engineers more weight to meet the SoC verification challenge head-on."
About Accellera's PSL
PSL was developed to address the limitations of current HDL languages in specifying design assertions. It enables the RTL designers to capture design intent in a verifiable form, while enabling verification of that intent with both the dynamic (that is, simulation) and the static (that is, formal) verifications. It also provides a standard means for hardware designers and verification engineers to rigorously document the design specification.
About Real Intent's Verix
Verix is Real Intent's pioneering assertion-driven formal verification system for exhaustively verifying that a design is free from complex, corner case errors that are hard to catch in simulations. Verix is the most easily deployable solution with its automatic setup and assertions. A suite of highly tuned formal engines, combined with a patented hierarchical formal verification, gives Verix the highest capacity in the industry.
Verix supports Accellera's Open Verification Library (OVL) and PSL as well as the IEEE standards for Verilog and VHDL (IEEE 1364 and IEEE 1076, respectively). Later this year, Real Intent plans to announce support for Accellera's SystemVerilog.
Price and Availability
Verix is available now with PSL support. Verix pricing starts at $75,000.
About Real Intent
Real Intent offers assertion-based formal verification products for electronic design. Its products are deployed at several leading semiconductor design companies in US, Japan and Europe. These products offer users the capability of comprehensively verifying designs early in the design process and significantly reduce the cost of verifying integrated circuits, electronic systems and systems on a chip (SoC).
Real Intent is located at 3910 Freedom Circle, Suite 102A, Santa Clara, CA 95054, tel.: (408) 982-5444, fax: (408) 982-5443, email: firstname.lastname@example.org, web: http://www.realintent.com.
Verix is a trademark of Real Intent Inc.
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