Virage Logic to Present Nanometer Design and Cost Management at DAC

5/27/2004 - Virage Logic (Nasdaq:VIRL), a leading provider of best-in-class semiconductor IP platforms, will share its experiences and insights on 90 nanometer (nm) design and its inherent yield and cost challenges at this year’s Design Automation Conference (DAC), to be held June 7 - 11 at the San Diego Convention Center.

In addition to in-depth presentations in its booth (#2941) and suites, Virage Logic will be co-hosting two key panel programs, one with TSMC and another with IBM and Chartered Semiconductor. Following is more detail on topics and panelists. For panel registration information, meeting requests, or to find out specific information on other Virage Logic DAC activities, visit the Virage Logic DAC online registration Web page:

TSMC & Virage Logic Breakfast Panel Session
Managing the Rising Design Costs of SoCs
This lively discussion will feature a broad range of executive-level perspectives from key stakeholders in the system-on-chip (SoC) supply chain. Co-hosted by TSMC and Virage Logic, the panelists will include: Chris Hamlin, LSI Logic; Dr. Edmund Cheng, Synopsys; James Wang, TSMC; and Adam Kablanian, Virage Logic. The panel will be moderated by EE Times Editor-in-Chief Brian Fuller. This event will be held Wednesday, June 9th, from 7:30 - 9:30 am, at the San Diego Convention Center, Upper Level (3rd Floor), Meeting Room 31B & 31C.

IBM, Chartered Semiconductor and Virage Logic Lunch Panel
The Brave New World of Nanometer Design
Virage Logic has assembled a knowledgeable panel of experts who will discuss the future of designing and manufacturing chips in the Nano Age. Co-hosted by IBM, Chartered Semiconductor and Virage Logic, the panelists will include: Jonathan Fields, Agere Systems; Mike Kerbaugh, IBM; Dr. John Martin, Chartered Semiconductor

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