Cadence Supports IBM-Chartered Process Platform with 90nm Reference Flow

5/25/2004 - Cadence Design Systems, Inc. (NYSE:CDN) announced the availability of a qualified design reference flow validated as compatible with the IBM-Chartered 90-nanometer process platform. The Cadence reference flow seamlessly integrates intellectual property (IP) developed by Artisan Components, Inc. for the IBM-Chartered cross-foundry design enablement program. Developed in conjunction with IBM, this RTL-to-GDSII reference flow -- based on the Cadence(R) Encounter(TM) digital IC design platform -- is optimized across the front-to-back design chain. It offers chip designers a predictable path for system-on-chip (SoC) design from RTL to first-pass silicon.

The reference flow incorporates leading Cadence technologies including Encounter RTL Compiler(TM) global synthesis, Encounter Test(TM) solutions, and NanoRoute(TM) unified routing and physical optimization.

"This reference flow is another significant step in the ongoing collaboration between Cadence and IBM. Cadence, Chartered and IBM customers will be able to use this reference flow to optimize their design process," said Tom Reeves, vice president, semiconductor products and solutions, IBM Systems & Technology Group. "It will enable a faster path to volume silicon using the leading-edge IBM-Chartered 90-nanometer CMOS process technologies."

The joint reference flow uses a wire-centric methodology to address key 90-nanometer SoC issues, including low power design, signal integrity, and design-for-test to provide the highest quality of silicon (QoS). QoS measures a design's physical characteristics using wires in terms of improved area utilization, higher performance and lower power consumption.

"The combination of advanced process technology, jointly developed by IBM, Chartered and leading-edge Cadence technologies, allows customers to benefit from improved quality of silicon resulting in reduced area, lower power and better performance," said Lavi Lev, executive vice president and general manager, IC Solutions, Cadence. "Ultimately, our goal is to provide mutual customers with a predictable path to first silicon."

"The Cadence Encounter platform focuses on some of the more challenging issues with regard to 90-nanometer design, and we're pleased to be collaborating with Cadence as a means for customers to accelerate their path to silicon," said Kevin Meyer, vice president of worldwide marketing and services at Chartered. "By leveraging the IBM-Chartered design enablement program, customers enjoy additional benefits such as design portability and a flexible sourcing model."

To access the 90nm reference flow kit, send an email to This reference flow kit contains a reference design, documentation and scripts to run the reference flow. Additional information on the reference flow can be found in the product brief at

Web Seminar
On Wednesday, June 30, 2004, Cadence, Chartered and IBM will hold a free webinar on how to enhance design team productivity and silicon reliability with the Cadence Reference Flow for the IBM-Chartered 90-nanometer CMOS process. To register or obtain additional information on this webinar, visit

About Cadence
Cadence is the largest supplier of electronic design technologies and engineering services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at

Cadence and the Cadence logo are registered trademarks, and Encounter, RTL Compiler(TM), Encounter Test(TM) solutions, and NanoRoute are trademarks of Cadence Design Systems, Inc.

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