Cadence Heads to DAC with Digital Nanometer SoC Design Flows

5/18/2004 - Design flows for digital nanometer design will be the key theme for Cadence at DAC, San Diego, California, 7 to 11 June 2004. TSMC and IBM will demonstrate RTL-to-GDSII 90 nm reference flows based on the Cadence Encounter platform.

Cadence will complete its Encounter platform for System-on-Chip (SoC) devices with the announcement of a global physical synthesis product, delivering the industry's fastest timing and signal integrity closure. The new tool extends the Encounter tool chain covering from either RTL or a logical netlist to placed gates.

With today's geometries, the percentage of total delay due to wire delay increases significantly. This makes traditional linear design flows obsolete, because you cannot afford to go all the way back and change the architecture or logic each time you encounter a problem at the physical implementation level.

Nanometer design also exacerbates physical effects known to introduce significant problems, notably signal integrity (SI) effects and IR (voltage) drop. Violations can surface late in the design cycle, delaying completion by weeks and requiring tedious manual repairs.

The Encounter platform replaces traditional linear design flows with a completely new design strategy that minimizes time to wires and full-chip iteration time. The platform also ensures the highest QoS. It provides a nanometer router that optimises wire creation for performance and manufacturability; a unified database with massive capacity of up to 50 million gates; and efficient extensibility.

Highly accurate silicon virtual prototyping technology also makes it fast and easy to model how very complex, high-performance chips will work in silicon. This prototyping allows you to explore the effects of changes and implement placement, floorplanning, and other critical back-end functions.

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