5/7/2004 - Cadence Design Systems, Inc. (NYSE: CDN) announced that leading technology companies, including Fujitsu Network Technologies and S3 Graphics, have adopted the Cadence IncisiveTM functional verification platform. These industry leaders report that the methodologies and technologies of the Cadence Incisive platform have enabled them to obtain significant productivity gains in the verification of complex, multi-million-gate system-on-chip (SoC) designs. The Incisive platform can compress overall verification time by as much as 50 percent.
The Incisive platform employs the world's first single-kernel architecture that overcomes fragmentation by unifying multiple verification techniques around a single engine. The platform includes the Incisive unified simulator for verification of today's toughest designs, and the Palladium® simulation acceleration and in-circuit emulation engine that brings added verification speed and efficiency. The Palladium system can deliver 10,000 to 100,000 times faster simulation performance in emulation mode or in embedded testbench mode.
Also integrated into the platform is the Conformal® equivalence checking tool, which came to Cadence as a part of the Verplex Systems, Inc. acquisition in 2003. Conformal technology delivers the only complete equivalence checking solution available for verifying complex SoC designs from RTL to layout. "By buying Verplex, Cadence got a first-class company and tool," said John Cooley, DeepChip editor and author of the 2003 DAC Trip Report.
Located in Yokohama, Japan, Fujitsu Network Technologies, a design subsidiary of Fujitsu, deployed the Incisive platform to meet the aggressive design goals of creating a new voice and signal processor to diversify its product offering.
"We adopted the Cadence Incisive verification platform for its mixed simulation and testbench capability, based on SystemC and RTL-HDL," said Eisuke Yuri, senior engineer, Advanced LSI Development Department, Fujitsu Network Technologies. "Using the simulator, we could conduct our work seamlessly, without concern for code differences. The new Incisive flow reduced the verification portion of the project from two weeks to three days and eliminated the need for hand-coding and rewriting RTL."
"In-circuit emulation is critical to keeping S3 Graphics on top of the graphics acceleration market," said Michael Shiuan, vice president of engineering, S3 Graphics of Fremont, Calif., a leading supplier to the 3D-enabled PC graphics market it pioneered. "Palladium enhanced in-circuit debug capabilities and the in-circuit speed improvement helped our verification engineers to increase their verification productivity dramatically. The combination of speed and efficiency improvements is just what we expected when we invested in the Incisive platform."
"Leading design teams worldwide are already realizing the tremendous speed and efficiency gains that the Incisive platform offers," said Ping Chao, executive vice president and general manager, design and verification, Cadence. "Incisive adoption is exceeding even our optimistic expectations, with over 70 percent of our Q1 2004 verification business going to the Incisive platform versus our traditional verification point tools."
The 2003 DAC Trip Report
John Cooley has compiled his DAC Trip Report annually for almost a decade following the Design Automation Conference (DAC). The report contains solicited input from users of electronic design automation (EDA) tools and it runs the entire gamut of product categories throughout the design flow, from front-end to back-end. This year's report contains input from 492 designers. To read John Cooley's DeepChip 2003 DAC Trip Report in its entirety, including additional customers' comments on adoption of the Incisive platform, go to http://www.deepchip.com/posts/dac03.html. The report is broken down into 43 sections and spans a comprehensive 254 pages of user opinions on EDA tools.
The Cadence Incisive functional verification platform is the world's first single-kernel verification platform that supports a unified methodology from system design to system design-in for all design domains. It can deliver up to 100 times full-chip performance throughout the entire design cycle, and can compress total verification time by up to 50 percent. The Incisive platform architecture natively supports Verilog®, VHDL, SystemC, SystemC verification (SCV) standard, OVL, PSL/Sugar assertions, algorithm development, and analog/mixed-signal verification. The Incisive platform offers full transaction-level support, unified test generation, and Acceleration-on-Demand.
Cadence is the largest supplier of electronic design technologies and engineering services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.
Cadence, the Cadence logo, Conformal, Palladium and Verilog are registered trademarks of Cadence Design Systems, Inc. Incisive is a trademark of Cadence Design Systems, Inc. in the U.S. and other countries.
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