TI Achieves Impressive EEMBC Scores for TMS320C6413 DSPs

4/27/2004 - Delivering an objective and detailed measure of performance per dollar value within a high performance DSP platform, Texas Instruments (TI) (NYSE: TXN) nnounced that benchmark scores for its new TMS320C6413 digital signal processor (DSP), published by the Embedded Microprocessor Benchmark Consortium (EEMBC), achieved an impressive nine TelemarksTM per dollar. The C6413 DSP targets packet-switched telecom including video, data and voice over IP and other cost-sensitive, high performance applications. For more information on these scores, please see: www.ti.com/performancevaluepr.

Representing typical telecom device tasks, the C6413 at 500 MHz was evaluated utilizing the EEMBC Telecom Benchmark suite. Certified by the EEMBC Certification Labs, two categories of benchmarks were performed including an out-of-the-box C-compiler test which achieved a score of 13.5 TelemarksTM, comparing very favorably with standard RISC processors. But the real benefits of this highly-parallel architecture are demonstrated after employing C-level optimizations, where the score jumped to 263.3 Telemarks.

Customers evaluate devices based on a number of factors other than just price and raw performance. Application-specific benchmarks, such as these by EEMBC, give customers additional insight in terms of how a given processor will perform in their specific system.

"TI continues its stellar achievements in the DSP space with the addition of the TMS320C6413, bringing high performance at a lower price point with the C64xTM generation," said Markus Levy, president, EEMBC. "Given the low price point, this new 500-MHz chip provides excellent value when viewed in terms of both its out-of-the-box score and its C-level optimized score."

The 500 MHz TMS320C6413 includes a foundation of eight parallel functional units in the DSP core, over 256 KBytes of on-chip high-speed memory and tailored telecom peripherals, including two standard multi-channel buffered serial ports, two audio serial ports compatible with IIS and common stereo codecs, two IIC control serial ports and three general 32 bit timers to accelerate applications and processing of real-time data. The one millimeter ball pitch on the ball grid array (BGA) package facilitates four layer board routing to reduce manufacturing costs by enabling a lower number of electrical layers on the board. The device also features an on-chip oscillator to lower overall system cost by enabling developers to use a sub-dollar external crystal in place of an external oscillator costing several dollars.

"EEMBC benchmarks have provided TI with a great opportunity to independently demonstrate the superb performance and value of our enhanced VLIW DSP core," said Jackie Brenner, DSP technical benchmarks manager, TI. "With the unbiased aid of EEMBC Certification Labs, these benchmark scores independently demonstrate to our customers the excellent price/performance value of the C6413 device for their applications."

The EEMBC Telecom benchmarks suite consists of five algorithms that represent device performance in real-world applications. They include autocorrelation, fixed-point bit allocation, fixed-point complex Fast Fourier Transform, Viterbi GSM decoder, and convolutional encoder benchmarks for which individual scores with several data sets are rendered in iterations per second.

The 500 MHz C6413 DSP costs $28.95 (10Ku). Samples are available now with full production slated for September 2004. Detailed benchmark scores on the TMS320C6413 are available at www.ti.com/performancevaluepr and www.eembc.org.

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