Carbon Enhances DesignPlayer to Accelerate Verification Regression

4/21/2004 - Carbon Design Systems, a fast moving EDA company that reduces the time-to-profit for chip and systems companies by enabling pre-silicon system validation, announced enhancements to its DesignPlayerTM software that allow it to be seamlessly plugged into hardware regression environments, be driven by a variety of testbenches, and provide a 10X or greater performance gain over current solutions. "Carbon's technology improved our regression performance by a factor of 10X over current simulators," commented Michael Shiuan, VP of Engineering at S3 Graphics.

DesignPlayer improves regression performance for verification environments, which may include standard testbenches such as: Vera, Verisity, transaction-level, behavioral Verilog, C, C++, and SystemC. In addition, DesignPlayer adds interoperability with popular simulators including those from Cadence and Synopsys.

"With this release, Carbon is building on its fundamental values of performance, accuracy, and broad applicability," said Steve Butler, president and chief executive officer at Carbon. "Carbon can now be used across the board for early stage hardware regression, pre-silicon software validation, and complete system validation."

Carbon's DesignPlayer is a cycle and register accurate runtime model of a chip or IP (intellectual property) core compiled directly from RTL. Software drivers, diagnostics, and firmware can be validated up to 50X faster on Carbon's DesignPlayer engine compared to an event-based simulator. Carbon's new release extends DesignPlayer into hardware verification regression environments in multiple ways.

What's New-DesignPlayer Addresses Verification Regression
Engineers that apply behavioral Verilog, Vera, or Verisity-based testbenches in a simulation regression environment improve their performance by simply plugging in an optimized DesignPlayer to replace their RTL model. This release allows DesignPlayer engines to plug-and-play with popular simulators including Cadence Incisive and Synopsys VCS. Verification teams using DesignPlayer with C, C++, or transaction-level testbenches (without a simulator) can achieve a 10-20X regression performance boost over RTL simulation, while maintaining cycle and register accuracy.

Designers that use SystemC to simulate fast abstract models of their design early in the development cycle, face a daunting simulation performance problem as RTL implementation models are substituted for their abstract counterparts. Simulation performance-when it's needed most-drops tremendously. DesignPlayer now sports an automatically generated SystemC interface to allow it to be instantiated in a SystemC environment and provide an immediate 10-20X performance increase, without losing accuracy.

Pricing and Availability
Carbon's DesignPlayer products are shipping now with pricing based on an annual subscription volume model. DesignPlayer engines used for development are under $10,000 per seat for high volume purchases, while IP distribution versions approach $1000 per seat.

About Carbon
Carbon is delivering software products that enable pre-silicon system validation, where thousands of users can simultaneously develop and test software on the 'golden' RTL hardware implementation model. For the first time, critical foundation software-drivers, diagnostics, and firmware-runs at KHz execution speed on the 'golden' model with cycle and register accuracy. This opens the door for system validation and IP deployment to begin much earlier than traditional methods.

Carbon Design Systems, Inc. is privately held and funded by Matrix Partners, Flagship Ventures, and Commonwealth Capital. The corporate headquarters is located at 375 Totten Pond Road, Suite 100/200, Waltham, MA. 02451. Telephone: 781.890.1500, Facsimile: 781.890.1711, Email:, Website:

Carbon Design Systems and DesignPlayer are trademarks of Carbon Design Systems, Incorporated.

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