Sequence Receives Patents for Analysis and Optimization of Chip Design

4/19/2004 - Strengthening its leadership position in analysis and optimization tools for SoCs, Sequence Design, Santa Clara, Calif., announced that is has been awarded 4 additional patents by the U.S. Patent Office for key technologies in design analysis and optimization.

"The demand for these clock tree synthesis and optimization technologies has been driven by our major ASIC customers, as well as custom design houses," said Dave Allen, one of the authors of the patents and Sequence fellow and director of engineering for physical optimization. "These technologies further enhance the concurrent analysis and optimization solution we offer designers through CoolTime(TM) and PhysicalStudio(TM)."

The first patent, Patent No. US 6,698,006, "Method for balanced-delay clock tree insertion" permits designers to construct a clock tree with delay and skew values that can meet tighter timing constraints.

The second patent, Patent No. US 6,701,505, "Circuit optimization for minimum path timing violations" describes a technology that optimizes delay insertions for reducing a timing violation in a timing path.

The third patent, Patent No. US 6,701,507, "Method for determining a zero-skew buffer insertion point" computes a position for a zero-skew driver insertion point in an area occupied by nodes driven by the driver.

The fourth patent, Patent No. US 6,701,506, "Method for match delay buffer insertion" is a technique for "match-delay" buffer insertion provided to add delays at a node without changing the input capacitance of the node as seen by the upstream node.

With the award of these patents, Sequence has been granted 18 patents.

About Sequence
Sequence Design, Inc. enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence's power and signal integrity software give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of nanometer design.

Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 50 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections(TM) and Mentor Graphics' Open Door(TM) partnership programs. Additional information is available at

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