4/13/2004 - Magma Design Automation Inc. (Nasdaq: LAVA), a provider of chip design solutions, announced that Blast Fusion ®’s built-in parasitic extraction capability has been validated by TSMC for its 0.13-micron process. The extraction capability is an integral part of Magma’s RTL-to-GDSII design tool suite and provides accurate timing correlation between the IC implementation process and final silicon. The RTL-to-GDSII tool suite includes Blast CreateTM, Blast PlanTM and Blast Fusion APXTM.
Magma’s RTL-to-GDSII tool suite integrates all design and analysis engines into one system operating on a unified data model. This provides all the design and analysis engines with continuous access to complete design data, allowing them to make fast and accurate design decisions throughout the flow. The Magma system incorporates highly accurate extraction rules computed using Magma’s QuickCapTM, the gold standard for parasitic extraction. Magma’s extraction also includes modeling of process bias effects, on-chip variations (OCV) and metal fill to ensure highly accurate modeling of parasitic effects in nanometer designs.
“Our customers’ migration to nanometer process technologies is growing, and so are their demands for EDA technology that allows them to leverage it for their most complex designs. To meet these demands, Magma is working with industry leaders such as TSMC so our customers can access leading-edge technology,” said Michael Ma, vice president of business development at Magma. “Blast Fusion’s extraction capability is an integral part of Magma’s RTL-to-GDSII tool suite, allowing customers to achieve timing closure without having to take the design out of the Magma environment. By offering highly accurate parasitic extraction within the system, Magma shortens design cycles and enables customers to get to nanometer silicon faster.”
“Our validation of Magma’s extractor is in direct response to increasing requests from designers to support an extraction capability on our 0.13-micron process ,” said Genda Hu, vice president of marketing at TSMC . “As we move toward smaller geometries, the extraction accuracy of a design system is becoming more important.”
Teradiant Networks, a leading developer of networking semiconductors, is among the first to confirm the accuracy of Blast Fusion’s built-in extraction capability with 0.13-micron technology files made possible by the collaboration between TSMC and Magma.
“Teradiant has delivered a pair of multimillion-gate, 300 MHz chips designed with the aid of Blast Fusion, Blast Noise® and Blast PlanTM," said Satchit Jain, CEO of Teradiant Networks, a leading developer of networking semiconductors. " The alignment of Blast Fusion’s capacity extraction file with TSMC’s 0.13-micron process significantly reduces the design set-up and preparation time ."
Blast Fusion parasitic extraction rules are now available from TSMC to its customers. For more information, contact your local Magma sales office.
About Magma Design Automation
Magma provides leading software for designing highly complex integrated circuits while maximizing Quality of Results with respect to area, timing and power, and at the same time reducing overall design cycles and costs. Magma provides a complete RTL-to-GDSII design flow that includes prototyping, synthesis, place & route, and signal and power integrity chip design capabilities in a single executable, offering “The Fastest Path from RTL to Silicon”TM. Magma’s software also includes products for advanced physical synthesis and architecture development tools for programmable logic devices (PLDs); capacitance extraction; and characterization and modeling. The company’s stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at www.magma-da.com.
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