4/13/2004 - Cadence Design Systems, Inc. (NYSE: CDN) announced Toshiba America Electronic Components, Inc. (TAEC), has successfully implemented an 8-million-gate system-on-chip (SoC) using the Cadence® EncounterTM digital IC platform. The chip, a networking switch, has a maximum clock speed of 300MHz and was designed using the Toshiba 130nm TC280 technology with a flat design methodology. Cadence Encounter provides a fast route to quality silicon, particularly for complex, high-performance SoC designs. With this successful tape out, the Encounter platform has become a fully supported digital IC implementation platform for TAEC.
"We are very pleased with the results we achieved with the Cadence Encounter platform. We have successfully used the Encounter virtual prototyping and planning capabilities to enhance our SoC design productivity for the past two years. Encounter has provided us with a fully integrated design flow from prototyping through GDS with excellent performance and turn-around times for big, fast 130-90 nanometer SoC designs," said Shigenori Imazato, vice president of Engineering Design Centers, TAEC. "The Encounter technology, augmented by exemplary support by Cadence, allowed us to complete tape out of the SoC entirely within the Encounter platform. We will continue using the Cadence Encounter platform in production for TAEC designs."
In order to achieve the highest quality of silicon with the simplest design flow, TAEC used the Cadence SoC EncounterTM physical implementation tool and wires-first methodology. The SoC Encounter tool's unique high capacity and fast run times allowed the TAEC team to use a flat design methodology for a larger chip than would otherwise not have been possible.
"We are delighted to see Toshiba successfully implementing aggressive nanometer designs using the Cadence Encounter platform," said Wei-Jin Dai, platform vice president, digital IC implementation, Cadence Design Systems, Inc. "Toshiba is a highly valued customer for Cadence. This tape out underscores our ongoing commitment to customer success as measured in quality silicon."
About SoC Encounter
SoC Encounter offers an integrated, front to back digital IC implementation solution, including silicon virtual prototyping, physical synthesis, nanometer routing and sign-off quality signal integrity. By creating actual wires early in the design process, rather than estimates, SoC Encounter delivers high quality of silicon with greater predictability and shorter implementation cycles than older approaches.
Cadence is the largest supplier of electronic design technologies and engineering services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.
Cadence and the Cadence logo are registered trademarks and Encounter, SoC Encounter and NanoRoute are trademarks of Cadence Design Systems, Inc.
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