Leopard Logic Rolls Out Reference Design for Gladiator CLD

4/1/2004 - Leopard Logic, Inc. introduced a reference design to showcase its Gladiator CLD6400 configurable logic device in a PowerPC® companion chip application. The first design in a series of reference designs, it demonstrates the capabilities of the GladiatorTM CLDTM in a real-world application that is common to a number of vertical markets including networking, wireless and storage. PowerPC is the leading control plane processor in systems such as edge/access routers, storage switches and wireless infrastructure systems. The design is being shown at the Avnet Cilicon (booth 1126) and Leopard Logic (booth 720) booths at electronicaUSA in San Francisco (March 30 – April 1, 2004).

“Gladiator CLD is a new class of device built on disruptive technology. We created this reference design to visualize the capabilities of our devices so that system designers can easily see the power and value we can deliver to them,” said Chris Phillips, President and CEO of Leopard Logic.

The CLD6400 PowerPC bridge integrates a system level controller with a 133 MHz Power PC bus interface, a 266 MHz DDR memory interface, a triple-speed Ethernet MAC (10/100/1000), a high-performance AES block and common system interfaces such as Flash memory, UARTs and a PCI bus. The platform runs Linux OS. Customers can use this design as-is or easily modify and integrate other blocks needed for their application to create a part that meets their exact requirements and ships in a matter of weeks.

Partners for Success Several of Leopard Logic’s partners made significant contributions to implement the reference design. Avnet Cilicon provided guidance on the market applicability and target specification for the design. “Communication systems require high performance processors and flexible bridging and data processing engines. We have seen many customers looking for the right companion chips for the PowerPC devices we distribute. Gladiator CLD is an ideal platform to implement such designs,” said Warren Miller, Vice President of Technical Marketing at Avnet Cilicon. “This reference design and the IP available through Leopard Logic allows customers to get the exact configuration they need in a matter of weeks.”

Leopard Logic IP partners Eureka Technology, Mentor Graphics and Amphion Semiconductor contributed the IP required to implement the design. SET Engineering provided the system level integration and software expertise.

“This design was a real team effort and we were extremely pleased with the support of all our partners in making this happen,” commented Stefan Tamme, Leopard Logic’s Vice President of Sales and Marketing. “This reference design shows the power of partnering with industry leaders to achieve best-in-class results by leveraging the strength of the Gladiator CLD alliance.”

On-chip FPGA is Key to Fast IP Integration To meet time-to-market objectives and manage design risk, the use of IP-based design has become a cornerstone of modern design methodology. The key challenge to integrating IP from third parties or prior internal designs is to achieve a seamless integration layer that ensures proper interoperability between these blocks. While IP usually comes silicon proven and fully validated, the integration with other blocks introduces interoperability risk. Wrappers are needed to connect the IP blocks and adopt interfaces and bus standards.

The Gladiator CLD architecture with its high-performance mask-programmed fabric (HyperBloxTM MP) and the tightly coupled FPGA fabric (HyperBlox FP) is an ideal platform to support IP-based design. Proven IP blocks are implemented in the high-performance, low-power MP fabric, while the interface layer is done in the on-chip FPGA.

This approach enables customers to rapidly integrate IP cores from multiple sources by leveraging the on-chip FPGA to shorten time to market. The high-performance on-chip FPGA capability also provides support for evolving standards or interface protocols even after the product is deployed in the field. In addition, IP sub-system interfaces can be tuned and optimized on an application specific basis.

“System-level integration of IP cores is always the key challenge designers face,” said Michael Kaskowitz, General Manager of the Mentor Graphics Intellectual Property Division. “Mentor’s commitment to standards-based IP results in shorter time to market and reduced risk. Gladiator CLD provides designers with peace of mind when it comes to the integration layer by largely eliminating the design risk while delivering ASIC-like performance and IP protection for our IP cores.”

About Gladiator CLD
Leopard Logic’s patented technology features the industry’s first fully hierarchical, point-to-point interconnect, which is at the root of Gladiator’s superior speed, utilization, predictability and reliability. The SRAM based HyperBloxTM FP (field-programmable) fabric can be reprogrammed by the user anytime. The HyperBlox MP (mask-programmable) fabric uses the identical logic core cell architecture, but replaces the SRAM configuration with a single-layer mask configuration to achieve significantly higher density, increased performance and lower power consumption. The HyperBlox FP and MP fabrics are combined with optimized memories, multiply-accumulate (MAC) units and flexible high-speed I/Os. Leopard Logic’s unified design environment allows rapid timing closure at the designer’s desktop without tedious design iterations or exposure to deep sub-micron (DSM) issues.

The first member of the Gladiator CLD device family is the CLD6400, which provides 6.4M system gates, 2.3Mb of on-chip memory and 680 I/Os. Operating at a system speed of 500MHz, the CLD6400 offers a 32 GMAC/second DSP capability, has 16 on-chip PLLs and DLLs to drive global clocks and implement high-speed interfaces, and a maximum power consumption of 5 Watts. The CLD6400 is manufactured in TSMC’s 0.13 CMOS process on 300mm wafers to deliver high performance and reliability combined with low cost.

About Leopard Logic, Inc.
Leopard Logic is a fabless semiconductor company headquartered in Cupertino, California. Leopard Logic provides Gladiator CLD, a family of configurable logic devices that combine ASIC and FPGA technologies in a single device. This innovative combination increases performance, reduces power consumption and board space, and minimizes costs when compared to discrete FPGA and ASIC implementations. The devices can be used across a wide range of markets and applications that require flexible logic solutions, such as networking, storage and wireless. For more information visit our website at www.leopardlogic.com.

Leopard Logic, the Leopard Logic logo, Gladiator, CLD, HyperBlox, HyperRoute, HyperVia and ToolBlox are trademarks of Leopard Logic, Inc.

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