3/25/2004 - Cadence Design Systems, Inc. (NYSE:CDN) announced that Agere Systems (NYSE:AGR.A, AGR.B) now accepts netlists produced by Cadence(r) Encounter(tm) RTL Compiler synthesis for implementation in its application-specific integrated circuit (ASIC) design centers. Used throughout the silicon design chain by intellectual property (IP) vendors, IC, and ASIC designers, Encounter RTL Compiler synthesis works to increase overall chip speed, reduce turnaround time, and help customers achieve the highest quality of silicon (QoS). Encounter RTL Compiler synthesis is a key component of the Encounter digital IC design platform and a critical step in the fastest route to superior silicon.
"Agere is committed to providing our customers with access to their choice of the best design technology that will ensure smooth transition from netlist to successful tape-out.," said Don Friedberg, director of design methodologies for Agere. "Agere is pleased to add Encounter RTL Compiler to the list of tools we support."
The new generation technology behind Encounter RTL Compiler delivers global synthesis for timing closure using a unique set of global synthesis algorithms that maximize the performance of challenging designs. These algorithms identify key leverage regions in the design to optimize. The result is a superior netlist for routing the design in a shorter period of time. In some cases runtime can be up to three times faster compared to conventional flows. This supports Cadence's overall wire centric approach to design with the Encounter platform.
"Getting faster chip speed with smaller die size in less time is valuable to every design team. The superior RTL Compiler results on our high-density gigabit Ethernet switch, gave us a much shorter timing closure process than we expected, said Shankar Mukherjee, director of Ethernet switch development at Agere. "Having more margin on this complex multi-million-gate IC before place and route made our ASIC handoff much smoother."
"Agere's use of Encounter RTL Compiler is a testament to our mutual goal of providing customers with design solutions that allow them to achieve outstanding QoS in less time," said Dr. Chi-Ping Hsu, corporate vice president, synthesis solutions, Cadence Design Systems, Inc. "The new generation technology behind Encounter RTL Compiler enables significant timing closure improvements which are so critical to our customers' success."
Quality of Silicon
In nanometer design, every aspect of a chip's performance becomes dominated by interconnect-related effects, design rules, and failure mechanisms. In order to truly understand the physical properties of a design at 130nm and below, a new, meaningful metric for speed, area, power, and test must be applied. QoS is the new generation metric that exclusively handles measurements after wires.
Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.
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