TI to Ship 65nm Semiconductor Process Samples in First Quarter of 2005

3/24/2004 - Maintaining a two-year cycle between manufacturing technology generations, Texas Instruments Incorporated (NYSE: TXN) (TI) announced details of its 65 nanometer (nm) semiconductor manufacturing process technology that is expected to shrink equivalent 90nm designs by half and boost transistor performance 40 percent. TI's new technology can also reduce leakage power from idle transistors by a factor of 1000 while simultaneously integrating hundreds of millions of transistors that support both analog and digital functions in System on Chip (SoC) configurations. The company has 4 megabit SRAM memory test arrays functional today, and plans to sample a wireless product built with the new process in the first quarter of 2005.

"TI's 65nm CMOS process doubles the transistor density over our qualified 90nm production process and positions Texas Instruments for a leadership role in delivering the benefits of 65nm to customers early next year," said Hans Stork, chief technology officer, Texas Instruments. "Along with the tremendous increase in functionality TI will offer at 65nm with highly-integrated SoC designs, we are taking significant steps to lead the industry in managing the power those designs consume."

Low-power design has become a key concern for TI customers as multimedia and high-end digital consumer electronic features are integrated into products, such as wireless handsets, that are battery powered or sensitive to the heat generated by today´s highly complex processors. As part of a larger strategy to address this issue, TI will first introduce its SmartReflexTM dynamic power management technology at the 65nm node in chips for wireless applications. This innovative technology will automatically scale power supply voltage depending on user demands, thereby helping to control power consumption in devices like TI´s OMAPTM applications processors. Using SmartReflex technology, circuit speed is carefully monitored so that the voltage can be adjusted to exactly meet the performance requirements without sacrificing system performance. As a result, minimum power is used for each operating frequency, extending battery life and reducing the amount of heat produced by the device.

Multi-Discipline Approach to Power Management
Texas Instruments invests in its own semiconductor manufacturing infrastructure and closely links its process technology development and chip design methodology very early in the development cycle to leverage that expertise across its product portfolio. Power management is uniquely sensitive to both how semiconductor process technology is applied at the core transistor level, as well as at the circuit design level. Several innovative techniques are being applied at 65nm by Texas Instruments to reduce the power lost by transistors when they are idle, such as the time when a cell phone is in standby mode waiting for a call. Some of the 65nm innovations include back-biasing of SRAM memory blocks, retention flip-flop circuitry that allows the voltage to drop extremely low without requiring a rewrite of the logic, and SmartReflex circuits that dynamically respond to application demands with higher or lower voltages to either increase performance or reduce power consumption. In total, the 65nm power management innovations can deliver up to a 1000 times reduction in leakage power.

"TI´s advanced 65nm process gives Sun Microsystems the foundation to build next generation 64-bit processor designs that support our Throughput Computing initiative and UltraSPARC® roadmap," said Dr. David Yen, executive vice president, Processor and Network Products group, Sun Microsystems. "Beyond pure processing performance, power consumption becomes a more important metric every year. TI has shared its innovations at both the circuit and transistor level to help Sun Microsystems lead the way in addressing power management at both the chip and system level."

Flexible Process for SoC Designs
Improving on its 90nm process to fully leverage cost effective CMOS, TI will offer several optimized 65nm recipes to balance the unique needs of each end product or application. This is done through adjustments to the transistors´ gate length, threshold voltage, gate dielectric thickness or bias conditions, to name a few. The TI 65nm design library will offer circuit designers an unprecedented number of options with multiple different voltage transistors available for maximum design flexibility and optimization.

A very low power offering will extend battery life in portable products such as application rich 2.5 and 3G wireless handsets, digital cameras and audio players with increasingly sophisticated multimedia functions. A mid-range offering supports both DSP-based products and TI's high performance ASIC library for communication infrastructure products. The highest performance version, with transistor gates as short as 29nm, supports applications such as Sun Microsystems' next generation UltraSPARC processor-based servers. TI's highest performance CMOS logic relies on the very short gate length transistor and highly effective gate dielectric scaling to reduce capacitance and increase drive current. These are the primary factors in transistor switching speed, which in turn determines processor operating frequency.

TI continues to offer extremely dense embedded SRAM in the 65nm process, with the six transistors in a cell occupying less than half a square micron of area and 1.5 Megabits fitting in a square millimeter. An extremely small SRAM cell allows TI to integrate very large amounts of memory close to its processor cores, accelerating application execution. SRAM is also a very cost-effective embedded memory solution because it requires no additional manufacturing steps.

Process Leverages Latest Materials and Manufacturing Capabilities
The 65nm process includes up to 11 layers of copper interconnect integrated with a low-k dielectric, Organo-Silicate Glass (OSG), that has a k (dielectric constant) of 2.8. TI has introduced OSG across its entire offering at 90nm after first qualifying the material for production at 130nm. Low-k materials reduce capacitance and propagation delays within the interconnect layers of a device, boosting the overall chip performance. Other improvements combining to drive performance and minimize leakage in both the NMOS and PMOS transistors include process induced strain on the transistor channel during chip processing to increase electron and hole mobility, nickel silicide to lower both gate and source / drain resistance, and ultra-shallow source / drain junctions. A unique use of differential offset spacers allows independent optimization of the NMOS and PMOS transistors.

Analog and RF Integration
TI libraries support a range of different threshold voltage transistors that can be combined to optimize circuitry for power consumption or high performance; multiple high speed I/O interfaces, including SSTL, HSTL, LVDS, DDR II, and SerDes; and analog/mixed-signal macros using optimized analog transistors and high density MIM capacitors. For system-on-a-chip designs, especially those targeted toward portable systems where silicon area is a premium, integrating these analog functions can enable lighter-weight, less expensive, more mobile applications. For example, TI´s Digital RF Processor (DRP) architecture takes advantage of the very fast switching speed of CMOS, as well as precise analog components, to integrate wireless radio functionality in single chip solutions.

TI's 65nm process is being developed for both 200 mm and 300 mm production, with qualified production expected in late 2005. A technical paper on the 65nm low power process will be presented at the VLSI Symposium in Honolulu, Hawaii in June 2004.

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