3/12/2004 - Xilinx, Inc. (NASDAQ: XLNX) announced that they have successfully completed interoperability testing between Xilinx® Virtex-II ProTM FPGAs and the Intel® IXP2800 network processor. The interoperability between Xilinx and Intel products ensures high-speed telecommunication designers of electrical and protocol compliance between the two solutions.
“The interoperability of the Intel IXP2800 network processor and the Xilinx SPI-4.2 cores allows system architects to focus on system level aspects of the design rather than spending their time verifying connectivity,” said Doug Davis, General Manager Intel Network Processor Division. “This will help accelerate the development of Ethernet, Packet-Over-SONET, and ATM applications within the metro access and WAN/LAN equipment provider community.”
The Intel IXP2800 network processor provides flexibility for adapting to different protocols for a wide-variety of high performance applications including, Metropolitan Area Network (MAN) switches and routers, multi-service switches, and Internet-edge switches and routers. Running at speeds over 15 gigabits per second, the Xilinx SPI-4.2 core delivers a predefined OIF compliant solution that customers can immediately incorporate into their FPGA designs to shorten product development cycles.
“Successful high-speed validation of the SPI-4.2 interface between the Intel IXP2800 network processor and Xilinx Virtex-II Pro platform FPGAs implementing a SPI-4.2 IP core enables customers to confidently design next generation telecom systems in the shortest possible development time,” said Sandeep Vij, vice president of Worldwide Marketing at Xilinx.
As part of the interoperability testing, both the media and switch fabric (MSF) interfaces were tested on the processor. Various features of the SPI-4.2 solution have been emphasized. The Xilinx SPI-4.2 core features an optimized burst mode configuration for data transfers to the Intel IXP2800 network processor to ensure efficient use of the processor's memory space. Additionally, dynamic alignment compensates for up to 9 inches of trace variation between SPI-4.2 bus signals.
About SPI-4.2 Core
Standard POS-PHY Level 4 originated from the SATURN Development Group. It has since been standardized in the OIF as System Packet Interface Level 4 Phase 2 (SPI-4.2) and in the ATM Forum as Frame-Based ATM Interface Level 4 (FBATM-4). SPI-4.2/ PL4 is an industry standard multi-service system interface supporting OC-192, 10 Gigabit Ethernet and multi-channel configurations, including 2.5 Gbit/s OC-48, 622 Mbit/s OC-12 and Gigabit Ethernet, as required by the new generation of super routers and Layer 3 switches used in multi-service voice and data networks. Xilinx offers industry's leading SPI 4.2 solutions to support high-speed Packet-over-SONET (POS) Internet traffic as well as 10 Gigabit Ethernet, Gigabit Ethernet and Asynchronous Transfer Mode (ATM) applications.
License Price and Availability
The SPI-4.2 single and multi-channel cores are available now for purchase as Xilinx LogiCORE products and are optimized for Virtex-II family of FPGAs and design tools. Pricing for the cores are $18,000 each. Licensing information can be found at the Xilinx IP Center at www.xilinx.com/ipcenter. The SPI-4.2 cores are sold under the terms of the SignOnce IP License, a single set of terms for licensing FPGA-based IP cores from Xilinx and over 25 third-party providers. For more information visit www.xilinx.com/ipcenter/signonce.htm.
Xilinx, Inc. (NASDAQ:XLNX) is the worldwide leader of programmable logic solutions. Additional information about Xilinx is available at www.xilinx.com.
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