Altera Discusses ASIC and FPGA Design Flow Synergy at SNUG

3/12/2004 - At the Synopsys User Group (SNUG) San Jose 2004, John Daane, President, Chief Executive Officer, and Chairman of the Board, Altera Corporation (NASDAQ: ALTR), will present how Altera and Synopsys have partnered to integrate ASIC and FPGA design flows into a unified development environment that is fully compatible with Synopsys Design Compiler®. This design methodology, combined with Altera's FPGAs and HardCopyTM devices, reduces design time, minimizes risk and provides an excellent solution for system requirements.

Altera will also be demonstrating the following technologies at the vendor fair:

March 15-17, 2004

Risk Reduction in Digital Design
March 16, 2004
4:05 p.m. 4:35 p.m.

Design Once: Unified Flow for ASIC and FPGA Design
March 16, 2004
10:45 a.m. 12:15 p.m.

SNUG Partner Review
March 16, 2004
6:05 p.m. 8:30 p.m.

Booth #36
Santa Clara Marriott Hotel
2700 Mission College Boulevard
Santa Clara, CA 95054 USA
(408) 988-1500

For Additional Information:

Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries.

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