3/9/2004 - Cadence Design Systems, Inc. (NYSE: CDN) announced the new Cadence® Allegro® system interconnect design platform to optimize and accelerate high-performance, high-density interconnect design. The Allegro platform delivers proven, best-of-breed design and analysis tools to support a new generation co-design methodology that promotes collaboration across the entire system design chain. Electronics manufacturers will benefit from the Allegro platform's ability to minimize design iterations within and between the design domains of IC, package, and PCB design. The new platform provides a common constraint-driven flow across design entry, signal and power integrity, and comprehensively addresses the implementation of system interconnects. Illustrating this new co-design methodology, Cadence is introducing a new approach to silicon design-in kits with its PCI Express design chain.
"Feedback from our IC and systems customers has clearly shown that the system interconnect design between today's complex ICs is a major bottleneck, delaying time-to-market. The Allegro platform provides an optimized, high-performance solution to that problem that delivers significant time and cost savings," said Lavi Lev, executive vice president and general manager, Cadence Design Systems, Inc. "Combined with the Cadence Virtuoso® and EncounterTM platforms, Allegro enables customers in the semiconductor and systems space to overcome the inherent challenges of design chain collaboration and high-speed system interconnect design."
System Interconnect Defined
The term "system interconnect" refers to the logical, physical, and electrical connection of a signal, its associated return path, and power delivery system. It travels between different IC I/O buffers and traverses die bump pads, package substrates, connectors, and PCBs. Design and analysis of the system interconnect is often performed using a highly-fragmented set of design processes across three different fabrics: IC, IC packaging, and PCB.
Virtual System Interconnect Co-Design Methodology
The Allegro platform supports a pioneering co-design methodology that provides for the design, modeling, and analysis of the system interconnect across all three fabrics. The methodology takes the system interconnect from specification through exploration, design, implementation, verification, manufacture, and correlation.
At the heart of this methodology is a virtual system interconnect (VSIC) model defined by Cadence that describes the entire interconnect. The VSIC model is used to capture the original design intent and is matured throughout the design process as various segments of the interconnect are implemented. Through the VSIC model, engineers can design and implement their portion of the system interconnect within the context of the whole.
IC/Package Co-Design—No Longer the Missing Link
The critical missing link in system interconnect design has been between the IC and its package. The Allegro Package Designer and Allegro Package SI are new generation technologies that support the feasibility analysis and design of the IC's bump array or die pads—taking into account I/O buffer placement, package technology rules, and electrical performance targets. The Allegro Package Designer also supports an engineering change process which ensures that the interface between IC and package is exactly the same in both design domains, eliminating the risk of mask re-spins.
"Silicon packages, be they for System-on-Chip or System-in-Package, demand increasingly higher integration and a greater need for system interconnect co-design and analysis across the entire design chain", said Bret Zahn, Vice President of Design and Characterization of ChipPAC. "ChipPAC's leading edge packaging technology and emphasis on developing enhanced semiconductor solutions is greatly benefited by the Cadence Allegro platform because it allows for quick feasibility, modeling and analysis of the system interconnect across the IC, its package and the PCB, bringing time and cost savings to our customers."
Key Capabilities of the Allegro Platform
The Allegro platform brings together all of the existing Cadence technologies for IC package and PCB design, including the Allegro PCB SI, an integrated high-speed design and analysis environment for engineers creating complex digital PCB systems and IC package designs. The platform also includes a common constraint management system integrated across hierarchical schematic capture, high-speed design and analysis, and the world's leading IC package and PCB layout systems.
PCI Express Design Chain Speeds Time-to-Profit
The Allegro platform will bring many benefits to the electronics industry. One area that will be positively impacted is the PCI Express technology solutions development effort. The PCI Express design chain is a VSIC model for a category of PCB implementations based around the Allegro system interconnect platform. It will be used as a design starting-point by systems companies and refined as the actual PCB interconnect is implemented. By working closely with its IC and system customers, Cadence is enabling design chain collaboration between IC providers and systems customers.
"Until now, EDA solutions have been lacking the ability to support collaboration between IC, package, and PCB design teams. The Cadence Allegro platform addresses these co-design issues head-on," said Vince Hu, vice president of technical services, Altera. "Altera is excited to be a part of the Cadence PCI Express design chain, which will accelerate our mutual customers' efforts to successfully implement designs using the PCI Express system interconnects and Altera FPGA devices."
The design chain also supports the plug-in of silicon design-in kits for specific ICs. With this release, customers can design with Intel's next-generation chipsets, Altera's Stratix GX FPGA, and the Cadence Services PCI Express Serdes. To learn more about the PCI Express design chain, please visit www.allegrosi.com.
Pricing and Availability
The Cadence Allegro platform supports Windows, Sun Solaris, HP-UX, IBM AIX, and Red Hat Linux platforms. Specific operating system support varies by product. U.S. pricing for a 1-year license starts at $54,000 for the Allegro Package Designer, $45,000 for the Allegro Package SI and $25,200 for the Allegro PCB SI. The platform also includes enhanced versions of all existing products, such as Concept® HDL, SPECCTRAQuest®, and the Allegro platform. The PCI Express design chain for use with the Allegro PCB SI is available for free downloading at www.allegrosi.com.
Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.
Cadence, the Cadence logo, Allegro, and Virtuoso are registered trademarks of Cadence Design Systems. Encounter is a trademark of Cadence Design Systems.
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