3/8/2004 - AMIRIX Systems Inc. announced that it has delivered a dual processor system with four Gigabit Ethernet (GE) ports based on its AP130 PCI Platform FPGA Development Boards. This system will be used by researchers at École Polytechnique in Montréal to investigate various network topologies, starting with a two dimensional mesh.
The AP130 is, at present, the largest member of AMIRIX's AP100 family of PCI development boards featuring the Virtex-II ProTM Platform FPGA, Xilinx's advanced FPGA, which incoporates as many as two PowerPC 405 hard cores. AP100 boards also contain SDRAM, Flash, support for 10/100 and Gigabit Ethernet, SystemACE/ CompactFlash interface, Multi-Gigabit Transceiver (MGT, a.k.a. Rocket I/O) support, and Expansion I/O. The AP100 supports an XC2VP7, XC2VP20 or XC2VP30 Virtex-II Pro, in an FF896 package. Versions supporting the XC2VP50 and XC2VP70 are currently under development.
AP100 boards come with the Baseline Platform preloaded in flash. The Baseline Platform is an FPGA configuration containing an SDRAM controller, UART, interrupt controller, OPB-External Bridge, and a stage one bootloader (based on PPCBoot) in block ram. Also preloaded in the flash is the PPCBoot monitor, a TimeSys certified Linux kernel, and a small root filesystem, for a truly out-of-the-box experience.
The AP100 ships with the AP100 Development Kit CD, which contains a BOM, schematics, user's guide, EDK 6.1 project source for the Baseline Platform, PPCBoot with source code, as well as Windows and Linux applications for controlling the board from a host over the PCI bus. Also included on the CD is a TimeSys Linux Board Support Package (BSP) for evaluation purposes.
The Dual Processor, Quad Gigabit Ethernet Platform
To support the research goals of École Polytechnique, AMIRIX developed an FPGA platform utilizing both PPC405 hard cores in the Xilinx Virtex-II Pro. The architecture provides both processors access to the SDRAM through a shared memory controller, which maintains private memory for each processor in hardware, as well as offering a shared memory space.
Each processor also has two Gigabit Ethernet Cores that include independent receive and transmit DMA engines, as well as mailbox and semaphore registers. As with the Baseline Platform, a UART and interrupt controller is provided for each processor and the OPB-External Bridge provides access to the flash memory. The stage one bootloader is stored in block ram and both processors use the PPCBoot monitor in flash. A Linux kernel with BusyBox based root file system is run on both PPC405 processors. The Linux OS includes the driver for the AMIRIX Gigabit Ethernet Core, as well as a shared memory virtual Ethernet driver for interprocessor communication.
The AP130 is enhanced with two additional Gigabit Ethernet PHY devices through the Expansion I/O port. A dual Gigabit Ethernet PHY mezzanine card is easily plugged onto the AP130 to provide a total of four high-speed network interfaces. The combination of this mezzanine card, the AP130 basecard, and the dual processor, quad Gigabit Ethernet platform provides the network building block for the various network topologies under investigation.
About AMIRIX Systems Inc.
AMIRIX's ability to offer fully integrated solutions through embedded hardware and software design provides significant added value for AP100. AMIRIX, a certified TimeSys Linux SDK developer, brings to the table an intimate knowledge of Linux, having ported Linux-based solutions to hardware in traditional embedded systems for several years. AMIRIX's extensive FPGA/PLD design experience has led to acceptance into the third party design service program of Xilinx as an XPERT Certified Diamond Partner. AMIRIX is ISO 9001:2000 certified. For more information on AMIRIX, the AP100, AP100 accessories, and Linux, please visit http://www.amirix.com/products.
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