2/20/2004 - Teseda(tm) Corporation and Agilent Technologies Inc. (NYSE: A) announced the first link that ensures transportability of Design-for-Test (DFT) data between engineering and production test platforms. Customers of the Teseda V500(tm) and the Agilent 93000 SOC Series can now quickly and reliably validate, debug, and apply IEEE 1450 (STIL)-based production test data generated by electronic design automation (EDA) tools. The net result is a test development flow that cuts weeks from time-to-money for many of today's semiconductor products.
"Supporting STIL transportability through our work with Teseda demonstrates Agilent's continued commitment to open systems and standards adoption," said Bill Martin, vice president of Agilent's SOC Consumer and Wireless Solutions Test. "Our DFT3 strategy, which builds on standards, tools and the Agilent 93000 SOC Series single scalable platform, delivers faster time-to-market and lowers cost of test."
"Many of our customers use the Agilent 93000 SOC Series for production test because of its scalability and flexibility," said Steve Morris, president and CEO of Teseda. "While the Teseda V500 is a DFT productivity tool that saves weeks when validating and debugging DFT, our customers still need to move large volumes of test data to their 93000s on the production floor as quickly and efficiently as possible."
Agilent and Teseda verified STIL transportability between the Agilent 93000 and the Teseda V500 using pattern files created by automatic test pattern generators (ATPGs) from leading DFT tool vendors, including Synopsys, Mentor Graphics, Cadence, and SynTest.
The STIL files were imported into the two systems and validated as equivalent. Pattern edits were made on the V500 and the revised patterns were output in STIL by the V500 and then read into the Agilent 93000; these patterns were also validated as equivalent. This process ensures that DFT tests that run on one system will also run on the other with equivalent results. An application note detailing the STIL transportability is available at both www.agilent.com/see/dft and www.teseda.com/pdfs/V500_93K_transport.pdf.
About the Agilent 93000
The Agilent 93000 SOC Series is the industry's fastest growing, lowest cost single, scalable platform with more than 600 installed systems worldwide. The Agilent 93000 SOC Series is designed to meet both the demanding performance and cost challenges of SOC testing. Models are configured to span the widest range of applications that may require ultra-high-speed digital data rates, up to 10 Gb/s, and the broadest range of mixed-signal and RF capabilities. With this range of capabilities, the 93000 SOC Series is the first choice for subcontract manufacturers (SCMs) and the preference for high-volume manufacturing. More information is available at www.agilent.com/see/soctest.
About the Teseda V500
The Teseda V500 is a DFT productivity tool for DFT-focused design validation, debug, and failure analysis. With its DFT-Optimized(tm) hardware architecture and DFT-Intelligent(tm) software system, IC companies around the world use the V500 to save weeks in getting their products to market, at a price that fits into an engineering productivity-tool budget.
About Agilent Technologies
Agilent Technologies Inc. (NYSE: A) is a global technology leader in communications, electronics, life sciences and chemical analysis. The company's 28,000 employees serve customers in more than 110 countries. Agilent had net revenue of $6.1 billion in fiscal year 2003. Information about Agilent is available on the Web at www.agilent.com.
About Teseda Corporation
Teseda Corporation is the leader in Design-For-Test (DFT) productivity tools that help semiconductor companies dramatically reduce test cost and cut weeks from time to money. Teseda is headquartered in Portland, Ore. For more information about Teseda visit www.teseda.com.
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