Celoxica Unveils DK Design Suite 3.0 with Re-timing Synthesis

2/16/2004 - Celoxica Limited announced the release of the DK Design Suite, version 3.0, extending the functionality of their high-productivity design environment for system FPGA devices. The latest suite includes the DK3 system design tool for synthesis of complex C-based algorithms directly to FPGA, Nexus-PDK3 for co-verification of hardware with software models and the PDK3 processor and board support packages for rapid system prototyping to hands-on hardware.

The new features in DK3 provide improved quality of results for the hardware implemented from C-based models. The Handel-C synthesis tool now performs re-timing of hardware critical paths, automatic use of FPGA combinatorial multipliers and on-chip resources, and automatic pipelining of synchronous memory blocks.

The new synthesis features give users the ability to perform speed/area tradeoffs directly from their C algorithms, realizing significant performance improvements of 100% or more without requiring changes to their source code. The Celoxica DK3 software continues to support all the latest FPGA devices from Altera and Xilinx and a number of other established and emerging reconfigurable architectures.

The latest features in version 3.0 of Nexus-PDK, Celoxica's co-simulation environment, include a new co-simulation manager that handles multiple simulation environments concurrently, manages data linking and global clocks across simulations, and eases user setup of the system co-verification environment. The Nexus-PDK environment supports co-simulation of cycle accurate C, C++ and Handel-C models with SystemC, MATLAB/Simulink, and VHDL and Verilog simulators.

The PDK3 processor support packages provide improved performance for processor cores commonly used in Altera and Xilinx FPGAs. The PDK3 Data Streaming Manager (DSM) API and simulation software supports ARM and NIOS processors in Altera devices and Microblaze and PowerPC processors in Xilinx devices. In addition the PDK3 board support package now includes a design wizard to help users easily set up board projects using Celoxica Platform Support Library (PSL) and Platform Application Layer (PAL) API libraries to speed up system prototyping and board reuse across projects.

The market acceptance of the Celoxica DK Design Suite was excellent in 2003. Celoxica maintained a 70% growth rate year over year and sold the 300th commercial DK license in 2003. "The new features in the DK3 release will only support that trend by making the design environment even more productive for implementing complex C algorithms in FPGA," said Jeff Jussel, vice president of marketing at Celoxica.

Pricing and Availability
The DK Design Suite Version 3.0 will be available for general delivery in March 2004. Version 3.0 will be available across all Celoxica product configurations with prices starting at U.S. $2000 for the Platform Developer's Package configuration. The software supports computing platforms with Windows 2000 and Windows XP. Celoxica also offers a broad range of signal processing IP, design services and off-the-shelf FPGA prototyping cards to support the DK Design Suite and the Software-Compiled System Design methodology.

About Celoxica
An innovator in system-level electronic design automation (EDA), Celoxica supplies the design technology, IP and services that define Software-Compiled System Design, a methodology that exploits higher levels of design abstraction to dramatically improve silicon design productivity. Celoxica's products address hardware/software partitioning, co-verification and C-based synthesis to reconfigurable hardware. Established in 1996, Celoxica offers a proven route from complex software algorithms to hardware, and provides an ideal design environment for System FPGA with significant productivity advantages for digital signal processing applications such as imaging, electronic security and communications. For more information, visit: www.celoxica.com.

Celoxica, Handel-C and the Celoxica logo are trademarks of Celoxica, Ltd.

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