2/6/2004 - Virage Logic (Nasdaq:VIRL), a leading provider of best-in-class semiconductor IP platforms, will take an active role in panel discussions at this year’s Design Automation and Test in Europe (DATE) conference to be held at the CNIT La Defense in Paris February 17–19 (http://www.date-conference.com). In addition, the company will announce new industry partnerships and highlight key customer successes in their booth, #2050.
Dr. Yervant Zorian, Virage Logic’s vice president and chief scientist, is the organizer of the DATE conference’s Executive Track program, which includes four sessions:
Managing Design Complexity in 90nm Technology
Semiconductor process technology has been advancing at a tremendous pace over the past decades. The 90nm technology will allow us to use hundreds of millions of transistors in a single design. How are we going to manage the design complexity? This session will allow a number of executives to address these challenges and the design methodologies needed to reach the necessary productivity. Adam Kablanian, Virage Logic’s president and CEO, will be a panelist in this session.
The Future of EDA: CEO Perspective
This executive lunch panel will provide the chance for DATE attendees to hear from the executives of the three largest EDA companies about their business perspective and corresponding R&D efforts, with some emphasis on the plans for “R” in the R&D.
Determining the Value of Test
Test has mainly been used to screen defective units to ship the remaining fault-free ones, thus considering test a technology with a negative impact on the bottom line. With the very deep sub-micron technologies, the impact of test is widening from a screening technology to one that helps debugging the first silicon, to a basis for repairing chips during manufacturing and in the field, to an infrastructure for diagnosis and fault tolerance. A number of executives in this session will discuss the value of test.
Advanced Solutions for SoC Design
System level design concerns are now dominating the definition of new platforms for future electronic systems. EDA tools need to address, on the one hand, the sub-nanometer physical design and manufacturability challenges and, on the other, move from the register-transfer-level to a higher level of abstraction, the electronic system level. The executives in this session will address the advanced solutions to achieve the above.
Jim Ensell, Virage Logic’s vice president of marketing and chairman of the Fabless Semiconductor Association (FSA) IP Committee, will also participate in the following panel session:
Common Ground for Measuring IP Quality
Since inception of the semiconductor intellectual property (IP) industry, providers and users have struggled to find a common set of metrics by which quality can be measured. For some, quality is borne out of the number of times a particular block has gone to volume production. For others, it is measured by the coding styles and validation practices used by the IP creator before releasing the core to market. Global semiconductor and system houses have spent significant time and resources in developing internal checklists, guidelines and measurements for internally created blocks but find that they are not always extensible for use when assessing externally created blocks. Industry organizations, EDA giants and standards committees have also tried to foster agreement on measurements. The differing definitions and weighted values can lead to protracted IP negotiations and is considered by some to be the root cause for stifled growth of the independent IP market. Panelists, consisting of IP consumers and industry organization representatives, will present their views of the evolution, progress and effectiveness of industry and individual company quality metrics. Particular attention will be given to the recent Quality IP (QIP) Assessment developed by the VSIA Quality working group and adopted by the Fabless Semiconductor Association.
About Virage Logic
Virage Logic Corp. (Nasdaq:VIRL) is a leading provider of best-in-class semiconductor IP platforms based on memory, logic, and I/Os that are silicon-proven and production ready. Virage Logic meets market demands for cost reduction, while improving performance and reliability for fabless and integrated device manufacturer (IDM) companies focused on the consumer, communications and networking, handheld and portable, and graphics markets. Virage Logic is headquartered in Fremont, California and has sales and support offices worldwide. For more information, visit www.viragelogic.com or call (877) 360-6690 toll free or (510) 360-8000.
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