2/2/2004 - To reduce time to market for a family of advanced networking silicon, Teradiant Networks built a single-pass design flow from best-in-class EDA vendors, and selected Sequence Design's CoolTime for signal-integrity signoff.
Using Sequence for final signoff does not extend time to market since the tool enjoys extremely fast runtimes, typically five to 10 times faster than competing products, and large capacities. It was also a simple matter to integrate CoolTime-SI within Teradiant.s existing flow thanks to tight links between Sequence and mainstream EDA tools.
More details on Teradiant.s use of CoolTime is available online: www.sequencedesign.com/images/success_stories/teradiant.pdf.
In addition to crosstalk-induced delay and glitch, CoolTime accounts for voltage-drop induced delays during timing analysis. CoolTime renders a complete timing and signal-integrity capability that accounts for on-chip and off-chip physical effects. With a built-in characterization engine for derating delays for voltage drop, CoolTime augments existing timing library formats for accurate timing analysis. An SDF output with voltage drop and crosstalk induced delays can be generated from CoolTime for signoff timing analysis.
Previous Page | News by Category | News Search
If you found this page useful, bookmark and share it on: