12/10/2004 - Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced the release of Active-HDL 6.3, Actel (Nasdaq: ACTL) edition. The new version provides easy-to-use push button integration to Actel's Designer series advanced place-and-route software. When combined with a third-party synthesis tool, Active-HDL and Designer create a complete design capture through physical implementation solution for Actel FPGA devices.
Complete FPGA Solution
When Active-HDL is connected with Actel Designer (aside from synthesis) the system becomes a closed environment to the engineer, complete with Actel precompiled libraries. It offers unrestricted VHDL, Verilog, EDIF or mixed simulation that is capable of executing all Actel implementation tools from the Active-HDL graphical user interface. The entire process from design capture, synthesis, implementation and optimization is handled directly from the Design Flow Manager. Active-HDL is compatible with most third-party synthesis tools from companies including, Synplicity, Magma, Synopsys and several FPGA vendor provided tools.
“The Active-HDL Actel Edition of our software provides the Actel FPGA designer with full access to unlimited simulation and debugging capabilities in a very easy-to-use closed environment,” stated Chris Erwin, product marketing manager for Aldec, Inc. Erwin added, “The automated Design Flow Manager along with precompiled Actel libraries and access to several synthesis tools completes the solution.”
"Actel is delighted that Aldec has chosen to release an Actel edition of its Active-HDL design environment," said Saloni Howard-Sarin, director of antifuse and tools marketing at Actel. "We value best-in-class, third-party tools, and Active-HDL provides a robust set of design and verification tools that are easy to use, flexible and powerful."
Design Flow Manager
Active-HDL provides access to several of the Actel physical implementation tools in the automated Design Flow Manager. These tools include the Actel Libero Integrated Design Environment, Silicon Explorer, ChainBuilder and FlashPro. In addition Active-HDL provides a Merge Design Files feature, which allows for multiple EDIF netlists to be merged together in the active design. Actel Designer can then import this netlist for physical implementation without leaving the Active-HDL environment. The Design Flow Manager supports Actel’s Designer series 6.0 and greater.
Actel's Designer is a premier design implementation software tool suite that offers an easy-to-use and flexible solution for all Actel FPGA devices. It gives designers the flexibility to plug and play with Aldec’s Active-HDL as well as industry-leading EDA tools from partners such as Synplicity, Mentor Graphics, Synopsys, Cadence, Magma Design Automation and many other top names in the EDA field. Designer's advanced place-and-route algorithms accommodate the needs of today’s increasingly complex design and density requirements. The architectural expertise built into Designers tools enables the user to create optimal designs. Actel's Designer software interface offers both graphical and scriptable flows in order to accommodate your design environment. Graphical device optimization can be done through the MultiView Navigator (MVN) and Timer interfaces. These interfaces provide expert users with maximum flexibility to drive the place-and-route tools to quickly achieve timing closure.
Active-HDL is a Windows®-based, completely integrated, high performance HDL design and simulation environment. It supports VHDL, Verilog, SystemC and EDIF from design entry through implementation. Active-HDL provides the fastest simulation runs for all designs, regardless of source language or target silicon, including those with embedded devices.
The product conforms to IEEE standards for VHDL and Verilog and provides a complete Actel FPGA solution. Active-HDL 6.3 AE, which is available today, includes a multi-design workspace, HDL editor, state machine editor, block diagram & schematic editors, automatic testbench generation, simulation design profiler, signal agent, waveform viewer, SystemC and a choice of VHDL, Verilog or mixed-VHDL/Verilog/EDIF simulation. Active-HDL 6.3 AE is sold directly from Aldec and all sales include one year of product maintenance. For a FREE evaluation copy, please visit our company’s website at www.aldec.com/ahdl.
Aldec, Inc., a 20-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs with its offices located around the globe. Continuous innovation, superior product quality and a total commitment to customer service comprise the foundation of Aldec’s strategic objectives. Additional information about Aldec is available at http://www.aldec.com.
Active-HDL is a trademark of Aldec, Inc.
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