11/19/2004 - Mentor Graphics Corporation (Nasdaq: MENT) announced that Toshiba Corporation has achieved significant success in the adoption of analog/mixed-signal HDL language, Verilog-AMS, for the design and verification of complex analog and mixed-signal LSI (large scale integration) designs. The Verilog-AMS support in Mentor Graphics® mixed-signal simulator tool, ADVance MSTM, allows the functionalities of LSIs to be validated earlier and more efficiently through the design cycles. Toshiba intends to continue deploying the ADVance MS tool in other projects to reduce the turn around time of their LSI designs.
“System verification for analog/mixed-signal LSI is becoming more challenging than ever due to the increasing circuit complexity,” said Mr. Takao Ito, senior manager of analog design CAD department, System LSI second business unit, Toshiba Corporation Semiconductor Company. “Through high quality behavioral modeling in Verilog-AMS and good collaboration with Mentor, we were able to accomplish great results in the top-down design and bottom-up verification methodology with the ADVance MS tool. It is important to expand this methodology to other application areas to continue offering high quality analog/mixed-signal LSI to meet our customer’s requirements.”
“Efficient analog/mixed-signal verification is important in the design of reliable products. It becomes even more critical when high-quality complex analog/mixed-signal SoC is demanded under short time-to-market pressure,” said Mr. Takeshi Yamamoto, manager of System LSI first unit, Toshiba Corporation Semiconductor Company. “The analog/mixed-signal language-based design approach, with the ADVance MS tool and Mentor’s CommLib behavioral model library, enabled efficient analysis of large circuits, while traditional analog or mixed-signal simulator did not go well. In addition, the availability of fast-Spice simulation technology, the Mach TATM tool, under the ADVance MS tool allows sophisticated analysis to be completed overnight.”
The Mentor Graphics ADVance MS (ADMS) tool is a single-kernel, language-neutral functional verification environment for digital, analog, mixed-signal and RF circuits. This platform is built upon four high-performance, customer-proven simulation technologies: the EldoTM tool for analog, ModelSim® for digital, Mach for transistor-level, and the Eldo RF for radio frequency simulations. The ADMS supports most of the design languages, including VHDL, VHDL-AMS, Verilog, Verilog-AMS, SystemC, SystemVerilog, Spice, and C, for the design and verification of mixed-signal system, and SoC. ADMS has gained wide acceptance since its introduction five years ago. It is currently used in hundreds of customer sites.
“With Toshiba’s superior circuit design expertise and Mentor’s cutting-edge AMS modeling and simulation technologies, we have implemented a highly advanced, yet realistic, methodology based on top-down design and bottom-up verification,” said Jue-Hsien Chern, vice president and general manager, Deep Submicron Division, Mentor Graphics. “We believe that our collaboration with Toshiba will continue to benefit both companies.”
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $675 million and employs approximately 3,800 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/.
Mentor Graphics and ModelSim are registered trademarks, and ADVance MS, Mach TA and Eldo are trademarks of Mentor Graphics Corporation.
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