11/17/2004 - Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA de vices, together with Magma Design Automation Inc. (Nasdaq: LAVA), a provider of chip design solutions, announced the completion and immediate availability of the design flow interface between Active-HDL 6.3 and PALACE version 2.4. The integration of the two products automates the data exchange of graphical design capture, mixed VHDL and Verilog verification and physical synthesis providing an efficient, easy-to use solution for ActelTM, Altera® and Xilinx® designs.
Complete FPGA Design Flow
Aldec and Magma have worked together to implement a new design flow option in Active-HDL to utilize the functionality of PALACE for physical synthesis of FPGA designs. When the design flow for the physical synthesis tool is enabled, a window displays the physical synthesis option button that allows the designer to control the process performed by PALACE. When combined with the FPGA vendor-supplied or industry-supplied FPGA synthesis tools, Active-HDL and PALACE provide a fully integrated front-to-back tool flow that delivers higher quality results.
“The interface between Active-HDL and PALACE provides complete design flow management of large FPGA and PLDs, independent of the architecture,” stated Eric Seabrook, product marketing manager for Aldec. Seabrook added, “As designs continue to grow in complexity and FPGA users are becoming faced with the challenge of ASIC like flows, an automated data exchange between the tools becomes increasingly important.”
While PALACE focuses on optimization of the synthesized netlist and architecture-specific implementation, Active-HDL provides a graphical design capture, mixed-HDL simulation and debugging environment. Once the design is verified in Active-HDL, the RTL is synthesized and optimized using PALACE through the automated design flow manager.
“Aldec provides FPGA designers with a highly integrated environment to capture and verify designs,” said Behrooz Zahiri, director of product marketing at Magma. “Through Magma’s and Aldec’s collaboration, FPGA designers familiar with the Active-HDL verification and design flow can now take advantage of PALACE’s advanced physical synthesis and speed-grade improvements.”
Pricing and Availability
Active-HDL conforms to IEEE standards for VHDL and Verilog and provides a complete FPGA vendor independent solution. Active-HDL 6.3 has a starting price of less than $6,000 including the interface to PALACE, and is sold directly by Aldec in the U.S. and authorized international distributors.
Active-HDL is a Windows®-based, completely integrated, high performance HDL design and simulation environment. Active-HDL includes a multi-design workspace, HDL editor, state machine editor, block diagram & schematic editors, automatic testbench generation, simulation design profiler, signal agent, waveform viewer, SystemC and a choice of VHDL, Verilog or mixed-VHDL/Verilog/EDIF simulation. Active-HDL provides fast simulation runs for all designs, regardless of source language or target silicon, including those with embedded devices.
Magma’s PALACE physical synthesis tool addresses the high-performance requirements of today’s challenging FPGA designs. To produce superior quality of results with minimal effort, PALACE unifies logic synthesis and physical design and provides an efficient physical synthesis engine for FPGAs. It includes constraint-driven optimization, architecture-specific mapping, and unique support for multi-cycle on-chip communication. PALACE push-button physical synthesis has consistently demonstrated at least one speed-grade performance improvement over a wide range of FPGA architectures.
Aldec, Inc., a 20-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs with its offices located around the globe. Continuous innovation, superior product quality and a total commitment to customer service comprise the foundation of Aldec’s strategic objectives. Additional information about Aldec is available at http://www.aldec.com.
Magma provides leading software for designing highly complex integrated circuits while maximizing Quality of Results with respect to area, timing and power, and at the same time reducing overall design cycles and costs. Magma provides a complete RTL-to-GDSII design flow that includes prototyping, synthesis, place & route, and signal and power integrity chip design capabilities in a single executable, offering “The Fastest Path from RTL to Silicon”TM. Magma’s software also includes products for advanced physical synthesis and architecture development tools for programmable logic devices (PLDs); capacitance extraction; and characterization and modeling. The company's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at www.magma-da.com.
Active-HDL is a trademark of Aldec, Inc. Magma is a registered trademark and PALACE and “The Fastest Path from RTL to Silicon” is a trademark of Magma Design Automation.
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