11/8/2004 - Robert Blake, Altera’s vice president of product planning, will be in the panel discussion “ASIC, Structured ASIC, and FPGA: Defining the SoC Methodology,” examining each of these alternatives to the problems of fast time-to-market, low-cost, and shortened design time for rapid response to fast moving markets. In addition, Altera will be presenting a paper explaining how engineers can resolve FPGA design challenges with Altera’s complete DDR2 interface solutions to lower risks, maximize performance, and accelerate time-to-market. Also, stop by the Altera booth to see demonstrations of our memory interface portfolio on Stratix® II high-speed I/O and memory boards.
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