10/20/2004 - IDTTM (Integrated Device Technology, Inc.; Nasdaq: IDTI), a leading communications IC company, announced that it has expanded its portfolio of packet-exchange flow-control management (FCM) products to include a new multi-function suite of system packet interface (SPI) devices.
The packet-exchange family includes three products that solve myriad interconnect problems in Core/Metro/Edge-based networking markets. It comprises integrated solutions supporting 10 Gbps packet processing and offers a wide range of options for logical port density and buffering capabilities, ranging from low-latency SPI-4-to-SPI-4 switching through complex flow-control designs requiring SPI-4 data overbooking and aggregation.
Incorporating three SPI-4 ports, the packet-exchange products facilitate the use of the point-to-point SPI-4 interface standard as a highly flexible multi-point connection scheme. The devices can seamlessly connect multiple SPI-4 network hardware elements, such as network processor units (NPUs), co-processors, traffic managers, multi-gigabit framers and physical interfaces (PHYs), and switch-fabric interface devices. In fact, the SPI-4 packet-exchange devices represent the first family of SPI-4 devices implementing this architectural flexibility and the first series of devices allowing 16 or more logical ports of two SPI-4 interfaces to be combined in a third SPI-4.
“Following the recent introduction of our SPI-3-to-SPI-4 packet-exchange products, the new SPI-4 devices underscore our commitment to offering customers more efficient and highly integrated system-on-chip solutions for managing flow-control and solving interconnect problems in high-speed networking applications,” said Jeremy Bicknell, product manager for the flow-control management division at IDT. “With the breadth of solutions now available in our portfolio, we are well positioned to give network equipment designers the highly integrated products they’ll need that leverage high-speed interface standards, such as SPI-4, to accelerate packet processing.”
The IDT SPI-4 packet-exchange devices build on the proven SPI-4 implementation and packet fragment processor (PFP) design used in the 4 x SPI-3-to-SPI-4 device announced in May 2004. The internal bandwidth has been doubled, and flexible expansion capabilities have been added. Each device within the family is targeted at a specific application. The IDT 88K8486 is ideal for simple data switching and aggregation in applications where less than 16 channels, fast backpressure response and adequate buffers in the attached SPI-4 devices are available. The IDT 88K8487 is ideal for connecting two 24-port 10/100/1000 Ethernet MACs to a single SPI-4 NPU. For more demanding flow-control applications, the IDT 88K8483 is available for designs requiring additional buffering and packet processing due to traffic consisting of “jumbo” Ethernet frames. With the largest amount of internal memory in the product family, it is well suited for connection to devices that have a slow backpressure response due to long internal pipelines tending to create numerous “in-flight” packets.
The entire SPI-4 product family provides many options and flexibility for demanding applications. It doesn’t penalize customers who do not require the high logical port counts or large data buffers needed to deal with the more complex data-aggregation techniques used in many system architectures. The new devices enhance the packet-processing capability of systems based on NPUs as processing elements. Although an NPU might have sufficient capacity to regulate end-to-end traffic flow, the SPI-4 system backpressure creates “bursty” data that can interfere with the correct operation of these flow-control mechanisms.
Like all IDT packet-exchange devices, the SPI-4 family uses a backpressure scheme that tolerates a large range of logical port data rates. Backpressure schemes are accommodated using large but efficient buffers created from segmented memory. This results in faster response times and lower internal latency, while affording absorption of large external delays caused by data and flow-control pipelines in adjacent devices, such as packet-forwarding engines and PHY devices. The buffering capabilities absorb typical bursts of in-flight packets and prevent loss of information that might occur as a result of long flow-control response times. This backpressure scheme also helps to reduce the frequency of congestion and starvation cycles at points in the data path, resulting in more efficient flow of packet data.
The SPI-4 packet-exchange family offers a number of features, including the ability to perform an automatic dynamic de-skew of a SPI-4 ingress data channel and SPI-4 egress status channel over a wide 80-MHz to 450-MHz range. This feature centers ingress bits and words relative to the clock without intervention by the user. In addition, the family offers a high-speed transceiver logic (HSTL) interface to QDR II memory or HSTL local packet interfacing to an ASIC or FPGA, thus enabling the expansion of on-chip memory in applications that require additional buffering. Additionally, they offer a full suite of diagnostic counters and error simulators, which ease in-service diagnostics and automate system initialization operations.
As originally defined by the Optical Internetworking Forum (OIF), the SPI interface resides between the PHY device and remaining SONET/SDH system and separates the synchronous PHY layer from the asynchronous packet-based processing performed by the higher layers. SPI-4 was originally conceived to perform at 10G to support the aggregate bandwidth requirements of ATM and POS applications. SPI-4 has become a ubiquitous standard for multi-protocol communications devices operating at 10G bandwidth, including Gigabit Ethernet and 10 Gigabit Ethernet PHYs, switch fabric interface circuits (FICs), NPUs, security processors, storage processors, traffic managers, mappers, framers, MACs and PHYs.
Pricing and Availability
The IDT SPI-4-to-SPI-4 packet-exchange devices are priced at $110.00, $132.00 and $165.00, each in 10k quantities for the IDT88K8486/7/3, respectively. Sampling to lead customers will begin in Q1CY05. Click here for additional product information.
Flow-Control Management ICs
As a leading provider of innovative products for the communications market, IDT continues evolving its distinctive competencies in integrating advanced memory and logic architectures, creating a new category of value-added semiconductor solutions called flow-control management (FCM) devices. FCM products provide access and/or queuing for data streams between subsystems and explicitly assist with additional functions, such as policing, shaping, scheduling, or directing the data. FCM devices have extensive impact in communications subsystem designs, and also provide benefits in medical, video, and data acquisition applications. The devices replace traditional methods of managing the flow of data within a system — previously accomplished with multiple ASICs, FPGAs, and external SRAM, DRAM or FIFOs. The IDT FCM portfolio consists of devices that execute packet exchanging, queuing, and multiplexing functions. The packet-exchange products integrate switched interconnection, port aggregation and rate adaptation needed in many networking applications, such as VPN firewall cards, Ethernet transport and multi-service switches.
IDT is a global leader in preemptive semiconductor solutions that accelerate packet processing for advanced network services. IDT serves communications equipment vendors by applying its advanced hardware, software and memory technologies to create flexible, highly integrated products that enhance the functionality and processing of network equipment. IDT accelerates intelligent packet processing with products such as network search engines (NSEs), programmable content inspection engines (CIEs), flow-control management (FCM) ICs and its family of InterpriseTM integrated communications processors. The portfolio also comprises products optimized for communications applications, including telecom products, FIFOs, multi-ports, and timing solutions. In addition, the product mix includes high-performance digital logic and high-speed SRAMs to meet the requirements of leading communications companies.
Headquartered in Santa Clara, Calif., the company employs approximately 3,200 people worldwide and has a wafer manufacturing facility in Oregon, and test and assembly facilities in the Philippines and Malaysia. IDT stock is traded on the Nasdaq Stock Market® under the symbol “IDTI.” The company is included in the S&P 1000, which is a combination of the S&P MidCap 400 and S&P SmallCap 600 Indices, and is also part of the S&P SuperComposite 1500, which combines the S&P 500, MidCap 400, and SmallCap 600. Additional information about IDT is accessible at www.IDT.com.
IDT, Interprise and the IDT logo are trademarks of Integrated Device Technology, Inc.
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