1/30/2004 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design solutions, announced that Renesas Technology Corp., a semiconductor joint venture between Hitachi, Ltd. (TSE:6501, NYSE:HIT) and Mitsubishi Electric Corporation (TSE: 6503 ) has completed a 10-million-gate, 0.13-micron design using Blast Fusion® APX, Blast Noise® and Blast PlanTM. The chip will be used in high-end consumer applications and contains over 200 macros and more than 70 clocks, some of which run at 400 MHz.
Renesas decided to use Magma for this design based on Magma's integrated prototyping, hierarchical design planning and implementation technology. Magma's rapid and accurate prototyping provided early predictability, enabling faster timing closure. Blast Plan's physical implementation and unique abstraction technology allowed engineers to partition the design into just five large blocks. Blast Fusion APX and Blast Noise provided complete design closure resulting in fully functional silicon in the fastest possible time.
“Before starting this project we evaluated our point-tool-based flow and concluded that it would not provide us with the required predictability and turnaround time. Magma's solution demonstrated a clear advantage in capacity, runtime and quality of results, especially with such large and complex designs,” said Kazuharu Hirachi, executive manager, SoC Division , MCU & SoC Business Unit at Renesas Technology Corp. “With the Magma system's open and accessible architecture, the transition to the new flow was quick and painless. We are pleased with the quality of results and the super-fast turnaround time. We achieved on-time delivery of working silicon to our customer, which validated our decision to adopt Magma.”
“When transitioning to 0.13-micron and smaller process technologies, many companies like Renesas find that their conventional point-tool flows begin to fail,” said Mehrdad Shahabi, president of Magma Design Automation Co., Ltd. in Japan. “We're pleased that Renesas was able to leverage our integrated IC implementation solution to provide silicon success with this impressive design.”
Blast Fusion APX and Blast Plan: High Capacity, Predictable Timing Closure
The 10-million-gate Renesas design was implemented hierarchically using five blocks. Renesas utilized Magma's prototyping and massive placement ability to decide the design partitions and demonstrate that these blocks are capable of closing timing. These blocks were then implemented using Blast Plan and its GlassBoxTM abstraction technique. This data reduction technique produces very compact block representations that contain all the physical, timing, signal integrity and extraction data necessary for hierarchical design. Using these compact blocks, Blast Plan implements fast and accurate top-level chip assembly without consuming enormous amounts of memory. Blast Plan leverages the high capacity of Blast Fusion APX and Blast Noise to minimize the number of top-level blocks, making floorplanning easier and timing closure more predictable.
Magma's Blast Fusion APX shortens design turnaround time by using the FixedTiming® methodology to determine the optimal timing prior to detailed layout, and to deliver a final design that meets timing without iterations between logic and physical design. Magma's unified data model allows the different implementation and analysis engines in Blast Fusion APX to work concurrently with accurate and complete design information. This allows designers to complete higher-performance chips in less time.
About Magma Design Automation
Magma provides leading software for designing highly complex integrated circuits while maximizing Quality of Results with respect to area, timing and power, and at the same time reducing overall design cycles and costs. Magma provides a complete RTL-to-GDSII design flow that includes prototyping, synthesis, place & route, and signal and power integrity chip design capabilities in a single executable, offering “The Fastest Path from RTL to Silicon”TM. Magma's software also includes products for advanced physical synthesis and architecture development tools for programmable logic devices (PLDs); capacitance extraction; and characterization and modeling. The company's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at www.magma-da.com. Visit Magma KK on the Web at www.magma-da.co.jp.
Magma, Blast Fusion, Blast Noise and FixedTiming are registered trademarks and Blast Plan, GlassBox and "The Fastest Path from RTL to Silicon" are trademarks of Magma Design Automation Inc.
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