1/20/2004 - Cadence Design Systems, Inc. and 0-In Design Automation, Inc., the Assertion-Based Verification company, announced that they have combined efforts to provide superior verification solutions to the market. As a key component of this relationship, Cadence® will integrate and license 0-In's library of assertion checkers, protocol monitors, assertion synthesis, and assertion management technology. The combination of these capabilities with the industry-leading Cadence IncisiveTM functional verification platform provides customers with new generation technology to increase verification speed and efficiency.
Through the agreement between Cadence and 0-In, 0-In's library of verification IP, which includes over 70 pre-verified assertion checkers and over 25 proven protocol monitors, will be integrated with the Incisive platform. By using the assertion IP library, Cadence Incisive customers can specify assertions 10x to 100x faster than they can by using language-only approaches.
"Many of our customers are using 0-In assertion-based verification with the Incisive platform, so this was a natural next step," said Ping Chao, executive vice president and general manager of the Design and Verification division, Cadence Design Systems, Inc. "The integration of 0-In's leading library-based assertion approach with the Incisive platform will help designers and verification engineers verify faster, more efficiently and more thoroughly. The relationship with 0-In demonstrates our overall strategy of open collaboration with industry leaders to provide customers with the most critical solutions for their design and verification needs."
"The CheckerWare® library and assertion synthesis technology are perfect complements to the Incisive verification platform," said Steven D. White, president and CEO of 0-In Design Automation. "Our joint customers will benefit from the improvement in verification efficiency this collaboration delivers—from the specification level through to the implementation level."
The licensed assertion synthesis capability provides interoperability of assertion formats such as Property Specification Language (PSL), SystemVerilog Assertions (SVA) and the Open Verification Library (OVL). This allows heterogeneous assertions to operate natively on the Incisive unified simulator and PalladiumTM accelerator/emulator. Incisive customers will now have the flexibility to mix-and-match language-based and library-based assertions to best meet their verification goals.
The relationship between 0-In and Cadence also leads to enhanced structural coverage capabilities in the Incisive platform. Structural coverage complements functional coverage by monitoring implementation corner-cases, enabling measurement of total verification completeness by design teams.
0-In plans continuing development of its assertion-based verification offerings for the Incisive platform, including integration with and performance optimization for the Incisive unified simulator and the Incisive analysis and debug environment.
The Cadence Incisive functional verification platform is the world's first single-kernel verification platform that supports a unified methodology from system design to system design-in for all design domains. The unified methodology may be followed from the block-level, system-level, or anywhere in-between. Incisive delivers up to 100x full-chip performance throughout the entire design cycle, and compresses total verification time by up to 50 percent. The Incisive platform architecture natively supports Verilog® and its future extensions based on SystemVerilog, VHDL, SystemC, PSL/Sugar and Open Verification Language (OVL) assertions, algorithm development, and analog/mixed-signal verification. This architecture provides customers, IP partners, and EDA partners with the open-interoperability they need to interface easily with the Incisive platform. With full transaction-level support, unified test generation, and Acceleration-on-Demand, the Incisive platform delivers the fastest, most efficient verification in the industry.
About 0-In Design Automation
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution built on industry standards that provides value throughout the design and verification cycle—from the block level to the chip and system levels. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics based products. With approximately 4,800 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.
Cadence, the Cadence logo, and Verilog are registered trademarks of Cadence Design Systems. Incisive and Palladium are trademarks of Cadence Design Systems, Inc. in the U.S. and other countries. 0-In® and CheckerWare® are registered trademarks of 0-In Design Automation, Inc.
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