Mentor Gets Formal with Scalable Verification for Largest ASIC Designs

9/30/2003 - Mentor Graphics Corp. announced the FormalPro Multi-Processor (MP) equivalence checking product. The FormalPro MP features a new scalable distributed architecture that utilizes multiple central processing units (CPUs) to increase the capacity and speed of verification and regression runs. This is the first of several new product developments for Mentor Graphics in its portfolio of scalable functional verification technologies.

The FormalPro MP can accommodate large, complex chips using a single workstation with multiple CPUs, or multiple networked workstations, to verify designs of 130 nm and below. The FormalPro MP enables the performance on large multi-million gate designs to scale enabling verification of the largest designs today and in the future. The FormalPro tool is the first generation of high capacity equivalence checkers from Mentor Graphics and has long been the capacity leader for equivalence checking, capable of verifying (application-specific integrated circuit) ASIC blocks of up to 20 million gates without demanding identical hierarchies.

The first FormalPro customer to view this new enhancement is Scientific Atlanta, a leading supplier of digital content distribution systems, transmission networks for broadband access to the home, digital interactive set-tops and subscriber systems designed for video, and high-speed Internet and voice over IP (VoIP) networks.

"The Formal Pro tool is key in our design flow and it has delivered excellent results," said Maynard Hammond, principal engineer for Subscriber Networks, Scientific-Atlanta. "We look forward to leveraging its increased capacity and performance for more complex designs."

"The FormalPro MP's ability to distribute verification across multiple workstations allows for scalability for the most daunting customer challenges," according to Robert Hum, vice president and general manager of the Mentor Graphics Design, Verification and Test division. "Mentor Graphics is committed to delivering scalable verification solutions that grow with the needs of our customers."

Scalable Verification with Mentor Graphics
The FormalPro equivalence checker is a key product within Mentor Graphics scalable functional verification technologies. Mentor Graphics offers the broadest and deepest range of integrated solutions covering the entire spectrum of system design and verification: digital, analog, firmware and software. Mentor Graphics provides the technology breadth and depth to enable thorough verification at every stage: block, sub-system and full system, while supporting the leading industry standards to ensure verification reuse and minimal risk for reliable verification.

The FormalPro MP will be available in the fourth quarter of 2003. The FormalPro MP capability uses existing licenses of the FormalPro and will be available to all new and existing customers.

About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $650 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site:

Mentor Graphics is a registered trademark and FormalPro is a trademark of Mentor Graphics Corporation.

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