9/25/2003 - Mentor Graphics Corporation announced that Zoran Corporation, the leading developer of custom digital solutions-on-a-chip technologies for use in consumer electronics, has adopted Mentor's Calibre xRCTM tool as its internal standard for GDSII parasitic extraction.
Trends in integrated circuit (IC) design for nanometer process technologies are driving the need for more advanced post-layout analysis, which in turn, is driving the need for more accurate device-level data. With gate counts increasing, clock speeds accelerating, geometries shrinking, metal layers growing, and design cycle times getting shorter, a comprehensive approach to parasitic extraction is required to gain accuracy, performance and detailed analysis.
"Calibre xRC is the only tool that extracts both gate and transistor-level parasitic data from a GDSII environment. The sign-off procedure based on the extracted GDSII data is the most reliable and accurate way to validate the design performance," said Mrs. Noga Dayag, CAD manager at Zoran's operations in Israel. "In addition, it was easy to integrate Calibre xRC with our layout and static timing tools."
In 2001, Zoran standardized on the Calibre physical verification tool suite, Calibre DRCTM (design rule checking) and Calibre LVSTM (layout vs. schematic). With the adoption of Calibre xRC, Zoran gains the advantages of a single tool suite for physical verification and parasitic extraction, plus a tightly integrated LVS-extraction link that provides exact measurement of device parameters, with proper back annotation to the original source netlist.
"As Zoran develops next-generation products for the ever-changing consumer electronics market, they need EDA tools that offer scalability, capacity and performance," said Joe Sawicki, vice president and general manager of Mentor's Design-to-Silicon division. "With Calibre, they have a design platform that is engineered to keep them ahead of the technology curve."
The Calibre Design-to-Silicon Platform
In nanometer design, the handoff between IC layout and manufacturing has changed. In previous technologies, the handoff was a simple DRC/LVS check at tapeout. Now it is a multi-step process where the layout database is modified so the design can be manufactured. This presents a host of challenges. Issues arise concerning process effects, photolithography, data volumes and acceptable yield.
To meet these challenges, design teams rely on the integrated Calibre design-to-silicon platform, which includes physical verification, full-chip, transistor-level parasitic extraction, design for manufacturability (DFM), mask data preparation (MDP), optical proximity correction (OPC) and resolution enhancement technologies (RET).
The Calibre design-to-silicon platform of integrated tools is recognized as the industry standard worldwide to address the complexities of advanced IC design.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $650 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.
Mentor Graphics and Calibre are registered trademarks of Mentor Graphics Corporation.
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