Cadence Encounter Improves Timing and Placement, Speeds Digital IC Design

9/24/2003 - Cadence Design Systems, Inc. (NYSE: CDN) announced version 3.2 of the Cadence® EncounterTM digital IC design platform. With Encounter 3.2, Cadence delivers improved timing optimization and placement algorithms, together with new-generation technology that addresses concurrent chip-package design for very large, fast ICs. The result is more rapid design closure and shorter overall development times.

With the addition of RTL CompilerTM synthesis, Encounter has become the route to generating higher quality implementation from existing RTL. Encounter also interfaces directly to the recently introduced Cadence Virtuoso® custom design platform through the industry-standard OpenAccess database. This provides designers with open interoperability to move their designs back and forth between the Encounter and Virtuoso platforms with ease.

"We are impressed with the recent progress made within Encounter to support concurrent silicon-package design," said Rick Sergi, technical manager, IO Floorplanning Group at Agere Systems. "As partners with Agere in developing these new capabilities, Cadence has been extremely responsive in introducing tools that will facilitate a collaborative approach to design of the silicon-package interface."

Additional enhancements to Encounter 3.2 include ECO routing capability in NanoRouteTM, NanoRoute technology in virtual prototyping, and improved clock tree algorithms for high-speed designs. These are key enablers for designer productivity, reducing optimization cycles in timing-critical and noise-sensitive designs.

Ikanos Communications, developer of broadband access products with a new class of smart silicon solutions, used the Encounter platform to develop its next generation Chipset.

"We have a strong Cadence tradition at Ikanos. We have used Cadence's place and route solution to achieve first pass success on 8 chips over the last 3 years. Our Design team upgraded to SoC Encounter for the latest generation of chips in 0.13u. SoC Encounter enabled our hierarchical design implementation including complete design closure," said Anoop Khurana, Vice President of Engineering at Ikanos Communication. "We were worried about possible signal integrity issues due to complexity of our chip. SoC Encounter's SI-aware routing coupled with SI analysis decreased the number of SI violations to less than 30 per hierarchical block. These violations were fixed automatically before final tape out. Our team felt that having the same engine for SI checking during design implementation and final-signoff was a key advantage to successful design closure. SoC Encounter helped us produce working silicon, production released in Revision A, in a record time."

Design house Time to Market, Inc. (TTM) specializes in high-quality, reliable ASIC and FPGA design services, which they provide to growing numbers of the world's top system houses, cutting-edge communication industry suppliers and network start-ups. TTM's expert team of designers relies on Cadence's proven Encounter platform to deliver production silicon.

"Our tapeout experience with the Cadence Encounter platform has shown a consistent reduction in the number of timing iterations. This enables us to meet the schedule for all our high-end ASIC tapeouts," said Venkata Simhadri, TTM's president and CEO. "We recently taped out a multi-million gate, 130-nanometer ASIC running at 300 MHz. The Encounter platform helped us achieve timing closure very quickly. We used the complete SoC Encounter flow for floorplanning, timing closure, place-and-route, and SI analysis. We also taped out an eight-million-gate, 180-nanometer flip-chip ASIC with the Cadence Encounter platform by developing a flip-chip methodology around the Encounter platform. TTM is looking forward to more challenging tape-outs using the Encounter platform."

"Encounter 3.2 marks another step forward in our delivery of advanced EDA technology. We deliberately set out to build a system with best-in-class technology at the key tool nodes, which would apply first and foremost to high-end, large, hierarchical designs at 130 nanometers and below," said Wei-Jin Dai, vice president, chip implementation at Cadence. "We are very pleased with the continuing rate of customer adoption and successful tapeouts on aggressive SoC designs."

About Cadence
Cadence is the world's leader in electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,000 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at

Cadence and the Cadence logo,Virtuoso are registered trademarks and Encounter, RTL Compiler, Nanoroute, SoC Encounter are trademarks of Cadence Design Systems, Inc.

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