Mentor Provides Tests for Nanometer IC Design with TestKompress

9/16/2003 - Mentor Graphics Corp. announced that several electronics industry leaders have adopted the TestKompress® embedded deterministic test (EDTTM) tool for testing nanometer designs. Companies including AMD, Ricoh and Renesas and several other large U.S.- and Europe-based semiconductor companies have selected TestKompress to produce effective, high quality manufacturing tests for their next generation designs while maintaining or reducing test costs.

"Mentor's on-chip test compression technologies add great value to the chip developer's tool kit. Semiconductor companies cannot afford to compromise performance and functionality, but they also cannot afford to spend an exorbitant amount of time on a tester," said G. Dan Hutcheson, CEO of VLSI Research Inc. "On-chip compression technologies enable more stringent tests that are quicker, more efficient, and more affordable. This helps ensure delivery of high quality devices without compromising the bottom line."

The move to nanometer process technologies and the use of new materials can lead to an increase in speed-related and resistive-type defects and jeopardize product quality. To thoroughly test these devices, additional test methodologies - specifically at-speed tests - need to be applied which can increase test data volume by three to five times. This additional test data volume can dramatically affect test costs and cause companies to make tradeoffs in their test strategy that can compromise test quality. TestKompress enables semiconductor manufacturers to increase the quantity and quality of tests they perform while controlling test costs by employing the proven EDT technology to significantly reduce the amount of test data volume by up to 100 times.

"Designs are moving to smaller and more complex process technologies, posing a challenge for digital design and test engineers to ensure that devices are thoroughly tested," said Robert Hum, vice president and general manager of the Design Verification and Test division for Mentor Graphics. "We are committed to providing whole-chip test solutions that help improve test and device quality, and control - or even reduce - the cost of test. With TestKompress as the standard test solution for nanometer design, Mentor Graphics continues to lead the industry in innovative design-for-test solutions, offering the broadest portfolio of tools to ensure the highest quality results."

TestKompress fits into any scan-based design flow and uses the same commands and design rule checks as FastScanTM, Mentor's industry-leading automatic test pattern generation (ATPG) tool, featuring at-speed test capabilities, diagnostics, and FastScan MacroTest for testing small embedded register files. Using TestKompress requires no changes to the core or functional design, and because the tool is based on traditional scan and ATPG methodologies, users of FastScan and other ATPG tools can easily adopt and integrate TestKompress into their test strategy. Additionally, the tool offers a scalable test solution that will efficiently handle future designs in excess of 100 million gates.

"Unlike other industry solutions, TestKompress did not require us to modify our existing designs," said Zenji Oka, manager of CAD Engineering Section, Imaging System LSI Development Center, at Ricoh Co., Ltd. "With TestKompress, we have a scalable solution that efficiently handled our designs without requiring more design effort and intrusion. We can now reduce test data volume, and test time, ultimately enabling us to run more tests to improve quality."

About Mentor Graphics Design-for-Test Tools
Mentor Graphics provides the industry's broadest portfolio of DFT solutions for today's System-on-Chip and deep submicron designs, including integrated solutions for scan, ATPG, embedded deterministic test, advanced memory test, boundary scan, logic BIST and a variety of DFT-related flows. For more information visit

About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $650 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site:

Mentor Graphics and TestKompress are registered trademarks and FastScan and EDT are trademarks of Mentor Graphics.

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