9/11/2003 - Synopsys, Inc. (Nasdaq:SNPS), the world leader in semiconductor design software, announced that Agere Systems (NYSE:AGR.A, AGR.B) used Synopsys' GalaxyTM Design Platform, employing Physical Compiler® physical synthesis, AstroTM physical design, Star-RCXTTM parasitic extraction, and JupiterTM design planning solutions to tape out the 5G APP550 network processor in a 0.13-micron process.
"Agere needed a predictable, proven design tool with advanced timing closure support for our network processor," said Bill Burroughs, technical manager within the Multiservice Networking division of Agere Systems. "By using the physical implementation tools in the Galaxy Design Platform, we met our performance target with a significant improvement in the timing-closure interval. In addition, Synopsys gave us excellent support during the design process."
Agere's ASIC design flow is built around Physical Compiler for achieving rapid timing closure from a register transfer level (RTL) description to placed gates. Agere engineers used Physical Compiler's synthesis and placement together to obtain a timing-clean result in a short and predictable time.
The APP550 network processor was designed using Agere's systems-on-chip (SoC) design flow, which is built around Astro for physical implementation. The tight integration between Physical Compiler and Astro's signal integrity-aware routing allowed Agere to complete the network processor on-schedule and produce parts working to specification. Several first tier global computing and communications OEMs have already chosen the APP550 for their next-generation Multiservice Networking equipment. The Agere APP500 family of products are highly integrated network processors that have robust classification, AAL5 segmentation and reassembly (SAR), integrated world-class traffic management for multiservice applications, and on-chip Ethernet MACs.
"Agere's design success with its network processor and ASICs demonstrates why the Galaxy Design Platform is at the heart of physical design for today's highly sophisticated designs," said Antun Domic, senior vice president and general manager of the Implementation Group at Synopsys. "By providing common libraries, delay calculation and constraints with consistent timing, the Galaxy Design Platform provides fast and predictable turn-around time from design-to-results."
About Galaxy Design Platform
The GalaxyTM Design Platform is an open, integrated design implementation platform with best-in-class tools, enabling advanced semiconductor design. Anchored by Synopsys' industry-leading semiconductor implementation tools and the open MilkywayTM database, the Galaxy Design Platform incorporates consistent timing, signal integrity (SI) analysis, common libraries, delay calculation, and constraints from RTL all the way to silicon. The Galaxy Design Platform helps reduce design time, decreases integration costs and minimizes the risks inherent in advanced, complex semiconductor design.
Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for semiconductor design. The Company delivers technology-leading semiconductor design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and is located in more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
Synopsys and Physical Compiler are registered trademarks of Synopsys, Inc. Astro, Galaxy, Jupiter, Milkyway, and Star-RCXT are trademarks of Synopsys, Inc.
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