Toshiba Tapes Out 2.5-Million-Gate SoC in 4 Weeks with Magma Software

9/10/2003 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design solutions, announced that Toshiba Corporation, a leading semiconductor manufacturer, and Toshiba Microelectronics, a leading LSI developer, used Magma software to successfully tape out and achieve first-pass silicon success on a 2.5-million-gate, low voltage (under 1.2V), low-power and high-speed consumer application device. The complex system on chip (SoC) had more than 100 clocks with some running faster than 200 MHz. The chip was implemented utilizing Toshiba's TC280 (0.13-micron technology node) process and Magma's integrated physical, hierarchical and signal integrity design technology. Despite having to incorporate various operating modes, a lot of IP (including ROM/RAM) and difficult industry-standard interface, the Toshiba designers were able to implement the challenging design in just four weeks with Blast Fusion APXTM, Blast PlanTM and Blast Noise®. Blast Noise was instrumental in avoiding noise problems during implementation that could have jeopardized the schedule.

"Magma's Blast Fusion APX was able to take advantage of Toshiba's TC280, 0.13-micron technology node for this complex SoC design and close timing in all of various operating mode," said Kiyofumi Ochii, vice president and general manager of Toshiba Microelectronics. "We were able to complete all of the design's technical requirements from netlist to tape-out in just four weeks."

"We are pleased that Toshiba was able to achieve the design target and their customer's aggressive schedule with Magma's integrated system," said Mehrdad Shahabi, president of Magma Design Automation Co., Ltd. in Japan. "Our solution continues to enable our customers to deliver complex and challenging designs on time."

Integrated Physical Design and Signal Integrity Analysis & Repair Capabilities Speed Time to Tape-out
Magma's Blast Fusion system is based on the patented FixedTimingTM methodology, an approach that enables Magma's systems to predict circuit speeds prior to detailed physical design. The systems then use a series of design refinements during physical design to achieve a final timing that is very close to the predicted circuit speed. With predictable timing results, iterations can be eliminated and time to market can be significantly improved.

Magma's Blast Fusion APX, Blast Plan and Blast Noise systems are based on a single, unified data model architecture that contains all the logical and physical information about the design and is resident in core memory during execution. The various functional elements - such as the implementation engines for optimization, placement and routing, and the analysis software for timing and delay extraction - all operate directly on the unified data model without relying on file interfaces or APIs. This tight integration allows more accurate analysis of the design and enables the system to make rapid tradeoff decisions during the design process to optimize for better chip performance.

Leveraging this unique data model architecture, Blast Noise automatically analyzes and avoids crosstalk noise and delay violations throughout the flow without any time-consuming manual intervention. These unique capabilities reduced Toshiba's design closure cycle and enabled it to deliver the designs in just four weeks.

About Magma Design Automation
Magma software is used to design fast, multimillion-gate integrated circuits, providing "The Fastest Path from RTL to Silicon"TM and enabling chip designers to reduce the time required to produce complex ICs. Magma's ASIC products for prototyping, synthesis, and place & route provide a single executable for RTL-to-GDSII chip design. The company's Blast Create TM, Blast FusionTM, Blast Fusion APXTM, Blast PlanTM, Blast Noise®, Blast RailTM and Blast RTLTM products utilize Magma's patented FixedTiming® methodology and single data model architecture to reduce the timing-closure iterations often required between the logic and physical processes in conventional IC design flows. Magma also provides PALACETM and ArchEvaluatorTM advanced physical synthesis and architecture development tools for programmable logic devices (PLDs).

Magma maintains headquarters in Cupertino, Calif., as well as facilities in Los Angeles, Orange County and San Diego, Calif.; Boston, Mass.; Durham, N.C.; Austin and Dallas, Texas; Newcastle, Wash.; and in Canada, China, France, Germany, India, Israel, Japan, Korea, the Netherlands, Taiwan and the United Kingdom. The company's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at

Magma, Blast Fusion, Blast Noise and FixedTiming are registered trademarks, and ArchEvaluator, Blast Create, Blast Fusion APX, Blast Plan, Blast Rail, "The Fastest Path from RTL to Silicon", and PALACE are trademarks of Magma Design Automation.

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