8/7/2003 - 0-In Design Automation, the Assertion-Based Verification Company, announced that it has achieved record revenues for the fiscal year ending July 2003 with revenue more than double that of FY2002. This revenue growth for 0-In's Assertion-Based Verification (ABV) Suite reflects increased usage by existing customers as well as broader deployment across a wide range of new accounts.
The record results reflect 0-In's position as one of the fastest-growing EDA companies and continue a pattern of growth as 0-In enters its fourth full year of revenue shipments. In addition to the revenue increase, the company reported that order backlog nearly tripled in FY2003. The faster growth of backlog than revenue is due to major customers making multi-year commitments to the company and its products.
"These financial results are due to our great customers and the increasing criticality of assertion-based and formal verification products," said 0-In chairman and CTO Dr. L. Curtis Widdoes. "Companies designing complex chips need ABV to make their projects successful and we're pleased to see the market responding so positively to what 0-In has to offer."
The increased revenue was driven by a combination of new customers, adoption of new products by existing customers and wider usage in many accounts. First-time 0-In customers in FY2003 included Cray, Matsushita, Rambus, and many other leading design teams from companies in consumer electronics, communications, storage and computers.
"Our customers are the most advanced design teams in the world and we're energized every day by working with them," commented Dr. Widdoes. "New customers help us expand our understanding of the needs of the market, and we are also pleased that our current customers, including AMD, Hitachi, National, Sun and others, renewed their annual agreements and added additional new 0-In products to their configurations."
0-In also announced that 0-In founder Steven D. White has been named president and CEO. Prior to founding 0-In, Mr. White was vice president of design verification for Synopsys, Inc., where he re-defined the company's verification strategy. Before Synopsys, Mr. White co-founded Logic Modeling Systems with Dr. Widdoes. Mr. White succeeds Dr. Emil Girczyc, who resigned to pursue other interests but will continue with the company in an advisory capacity.
"I have the utmost confidence in Steve's ability to lead 0-In during this period of rapid growth in a key area of EDA," said Dr. Widdoes. "I also want to acknowledge the contributions Emil made during an important growth phase for the company. Under his leadership, 0-In greatly expanded its product line, transforming powerful technology and point solutions into a full suite of ABV tools. We will continue to benefit from his vision and technical insight in his new advisory role."
0-In's ABV and formal verification tools focus on the hardest verification problems in customer's designs, verification hot spots. Traditional simulation-based methodologies are inadequate to verify verification hot spots, which occur both at the interfaces and in the internal logic of blocks. There are simply too many transactions, combinations of transactions and variable delays to simulate such hot spots exhaustively. This is an example of the 80/20 rule: 20% of the logic accounts for 80% of the verification effort and 80% of the risk of a re-spin due to an undetected functional bug.
"Assertion-based and formal verification can provide a ten-fold increase in verification productivity for SOC and ASIC designs," said Mr. White. "0-In's ABV suite of tools enables a systematic methodology to provide verification sign-off for hot spots. This methodology can be adopted incrementally by design and verification teams, providing value at every step. Our strong financial results over the past year testify to the value of this methodology for leading-edge development teams around the world."
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle - from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
0-In® and CheckerWare® are registered trademarks of 0-In Design Automation, Inc.
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