Mentor Graphics Goes Global with Technical Forums

8/27/2003 - Mentor Graphics Corporation announced it is hosting a worldwide series of electronic design automation (EDA) technical forums for engineers working in the most challenging areas of design, including design-to-silicon, functional verification, field-programmable gate array (FPGA) design, printed circuit board (PCB) design, and design-for test (DFT).

The forums, held in the United States, Canada and Europe as well as Pacific Rim and Japan, offer technical sessions, hands-on tutorials, panels of industry experts and presentations from experienced EDA tool users. Forum keynoters include: Dr. Walden C. Rhines, chairman and CEO of Mentor Graphics®; Dr. Bernard Meyerson, chief technologist, IBM; Stanley Bruederle, vice president of research, the Gartner Group; Sir Peter Bonfield, member of the board of directors of Mentor Graphics, Ericsson, and TSMC; and Prof. Dr. Lothar Spaeth, former board chairman, Jenoptik AG.

For specific locations, and dates, go to

Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $650 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site:

Mentor Graphics is a registered trademark of Mentor Graphics Corporation.

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