8/19/2003 - Mentor Graphics Corporation, the market leader in printed circuit board (PCB) design solutions, announced the latest version of its FPGA BoardLinkTM tool, which automates the integration of FPGA and PCB design processes to reduce design times and enable electronics companies to capitalize on the latest advances in PCB and FPGA technology. FPGA BoardLink's automated synchronization takes only minutes to update the pin-out assignments based on the latest FPGA place and route results, replacing traditional manual processes that required days of designers' time. The new version of the FPGA BoardLink solution addresses the challenge of representing today's large, high pin-count FPGA devices by making it possible for PCB designers to partition or "fracture" them into smaller, more manageable symbols that can be schematically represented.
The FPGA BoardLink tool is available immediately and offered without cost to customers using the Mentor Graphics® Board Station® and ExpeditionTM PCB design flows. Part of Mentor's continued focus to address the most complex PCB design challenges with industry-leading technology and integrated solutions, FPGA BoardLink integrates Board Station and Expedition with the Mentor Graphics FPGA Advantage® integrated flow as well as design tools from major programmable logic vendors.
"FPGA BoardLink with fractured symbol support has enabled us to reduce the time taken to initially produce and iterate our schematic and PCB layout data for even modest size (200+ pin) FPGAs from two days to a matter of minutes," said Rob Davies, EDA System Manager for Honeywell Aerospace Yeovil. "As we move up to 1,000+ pins this software becomes an essential part of integrating FPGAs into our PCB layout flow."
Automatic Symbol Generation and Partitioning for High Pin-Count Devices
PCB designs are still largely schematic based and require a schematic symbol to represent each device in the design. Today's large FPGA devices are reaching pin counts exceeding 1,500, making it physically impossible to use traditional symbol creation and management techniques. The symbols for these large devices are too big to print on even the largest size drafting sheets and often violate corporate drafting standards.
"The advanced high-performance Virtex-II ProTM Platform FPGAs include packages that exceed 1,500 pins which must ultimately reside on a PCB," said Steve Lass, director of Software Product Marketing at Xilinx. "Our customers need to effectively migrate high-density FPGA designs to a PCB in an automated and reliable fashion without compromising time to market or FPGA performance. Mentor's FPGA BoardLink provides the FPGA to PCB connectivity our customers are asking for."
Mentor's BoardLink solution allows these large devices to be schematically represented by partitioning or "fracturing" them into smaller, more manageable symbols. Symbol fracturing is accomplished through a table-driven methodology on a per-device basis allowing for custom symbol generation. The fractures can be grouped by functionality or PCB design team boundaries. The fractures are then automatically merged and mapped to the FPGA package for PCB layout and simulation purposes.
"PCB technology and design system advances are enabling packages with pin counts exceeding 1,500 pins and sub 1mm pin pitches," said Bob Potock, director of engineering desktop solutions, systems design division, Mentor Graphics. "Our Board Station and Expedition customers are asking for improved FPGA design tool integration with Mentor's PCB design solutions. The latest enhancements to FPGA BoardLink represent a significant step in delivering those desired productivity gains to our PCB designers."
Managing FPGA Pin Assignments Changes
During speed optimization or logic changes, FPGA pin assignment modifications often require time-consuming manual schematic updates and PCB re-routing. Typically pin assignments change three to five times per design cycle. Each pin-out change can take days of PCB designer or librarian effort to resynchronize the PCB and FPGA design processes. FPGA BoardLink closes the design process loop by automatically updating the pin-out assignments for each symbol or fracture based on the latest FPGA vendor place and route results. This automated synchronization reduces into minutes manual processes that formerly consumed days.
Pricing and Availability
The FPGA BoardLink tool is available immediately and will be offered free of charge to Mentor's PCB design solution customers. Integrated with Mentor's Board Station, Expedition and FPGA Advantage solutions, the FPGA BoardLink solution also supports tools from the following vendors: Xilinx ISE Alliance, Altera Quartus and MaxPlus II, and Actel Designer. DxDesignerTM integration is planned for Q4 2003.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $650 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/.
Mentor Graphics, FPGA Advantage and Board Station are registered trademarks and FPGA BoardLink, Expedition, and DxDesigner are trademarks of Mentor Graphics Corporation.
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