7/31/2003 - Cadence Design Systems, Inc. (NYSE:CDN) and Global Unichip Corp., a dedicated one-stop full service SoC design foundry, have jointly announced that Global (Unichip) has selected the Cadence® Encounter® Digital IC implementation platform as Unichip's hierarchical IC implementation platform. This equips Unichip with the capabilities it needs to address nanometer design challenges in its customer design services — specifically, virtual prototyping, routing, signal integrity (SI) and timing closure issues. Cadence and Unichip teamed up on a methodology project to build this advanced tapeout flow.
Encounter Enables Concurrent Timing and SI Closure
Unichip utilizes the three integrated components in the Encounter platform to ensure both timing and SI closure in its nanometer hierarchical design flow. These components include First Encounter Ultra, NanoRoute® Ultra and CeltIC®. First Encounter Ultra enables a continuous convergence methodology which begins with silicon virtual prototyping (SVP) — a fast full-chip implementation including complete wires. SVP provides an accurate early view of a design's physical characteristics, enabling predictable implementation even of very large ICs containing many individual blocks and complex timing requirements. Unichip design teams can then fine-tune the SVP to complete the design, using the Cadence high-performance NanoRoute router, leveraging NanoRoute's concurrent gate and wire optimization features for accurate timing closure and SI prevention and repair.
To verify SI closure, Unichip engineers use CeltIC to detect crosstalk-induced failures from chip implementation through signoff. CeltIC delivers accuracy comparable to SPICE and reports 10-100x fewer false violations than competing crosstalk analyzers, thus greatly reducing the chip development cycle.
"As the leading design service company in the community, we fully understand the versatile challenges from the industries we serve," said KC Shih, vice chairman and CEO, Global Unichip. "Nanometer issues and customers' stringent time-to-market schedules are always tough challenges. That's why we partnered with Cadence to develop our hierarchical IC implementation flow. It is really impressive to see Cadence work with our team and complete such an advanced design flow. The Cadence Encounter platform enables us with a prominent timing and signal integrity closure flow with best signoff quality. We have already taped out many complex designs since last year."
"We are delighted that our Encounter platform has been selected by GlobalUnichip, and we see this is a great customer win," said Matthew Chan, president, Cadence Design Systems Asia Pacific Operations. "The Encounter platform enables our customers to get the most out of their silicon and get to silicon success faster and easier. More importantly, we are committed to closely support Unichip through to successful design tapeout. Our engagement with Unichip is yet another validation of customer endorsement of the Encounter Platform."
About Global Unichip Corp. (Unichip)
Unichip, a dedicated one-stop, full-service SOC design foundry, provides total solutions from silicon-proven IPs to challenging complex time-to-market SOC design, production and testing services. Unichip has state-of-the-art EDA tools, a proven very deep submicron design flow and experienced engineers, which provide customers quality and fast time-to-tapeout. Furthermore, Unichip provides a one-stop turnkey solution through its partnership with world-class assembly and testing houses. Today, Unichip has customers throughout Japan, Korea, China, North America and Europe. Its dedication in providing a one-stop, full-service SOC design foundry will benefit more customers from product concept to revenue shipment in the shortest time. In 2003, TSMC, the semiconductor foundry leader, became a major shareholder. With TSMC partnership, UniChip continues to excel to be the best SOC design foundry and solution provider. For more information, please refer to: www.globalunichip.com.
Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics based products. With approximately 5,000 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at http://www.cadence.com.
Cadence, the Cadence logo, Encounter, NanoRoute and CeltIC are registered trademarks of Cadence Design Systems, Inc.
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