Pentek Offers Pulse Compression IP Core for Radar Applications

7/29/2003 - Modern radar systems use pulse compression to increase range, resolution and accuracy. Implementation, however, has required a dedicated DSP or multiple intellectual property (IP) cores to handle the FFT, complex multiply and inverse-FFT operations involved. Now, Pentek has introduced a core design that integrates all three components into a single FPGA core.

Pulse compression radar uses a swept-frequency burst as the outgoing signal, delivering more energy on the target without increasing peak power. Correlating this longer outgoing pulse with reflected information in the return signal can dramatically reduce noise and interference. The result is a dramatic performance improvement in target acquisition, tracking and identification.

The approach has been in use for decades, but implementation had been a challenge until the introduction of Pentek’s 4954-440 Pulse Compression core for the GateFlow FPGA IP library. “We’re proud of this first, fully-integrated pulse compression IP core offering,” says Rodger Hosking, vice president of Pentek, Inc. “Instead of dedicating DSPs to handle FFTs or building and assembling multiple FPGA blocks from scratch, this extremely flexible and powerful core is ready to use and fits in a single Virtex-II, Virtex-II Pro or Spartan 3 FPGA.”

David Squires, director of the DSP Center of Expertise at Xilinx, notes that, "This specialized core is representative of the value that Xilinx's partners provide to the electronics community. Pentek has created an efficient, high-performance design that will reduce the time-to-market and development cost for anyone creating return echo processing systems such as radar or sonar.”

The Pulse Compression core provides design flexibility by offering developers three parameters for customization. The core is available optimized for maximum system throughput or for minimum FPGA resource utilization. In addition, designers can select 2k-, 4k-, 8k-, or 16k-point for the FFT’s maximum size and 16-, 20-, or 24-bits resolution. These three parameters thus make 24 variations that designers can use to match the core to their system needs.

The core utilizes a block floating-point architecture to gain the best features of fixed- and floating-point computation methods. Block floating-point sets the exponent of all data used in a given calculation to match the largest value in use. This makes the computation as simple to implement as a fixed-point architecture while preserving the dynamic range characteristics of floating-point. The result is a combination of high performance and minimal resource requirements. A maximum-speed core using an 8k-point FFT, for instance, will fit in a Virtex-II XC2V3000 FPGA yet can achieve a minimum frame spacing of only 225 µsec.

Design Support
Designers interested in the Pulse Compression core can download a behavioral VHDL simulation model. They can then employ ModelSim to test and simulate the functionality, speed and FPGA resource utilization for these cores, gaining a true representation of how these cores will behave in their designs. Evaluation Pulse Compression cores can be located at

To speed development once a version is selected, the core comes with an example project using a 4k-point, 24-bit version that designers can easily modify. In addition, a VHDL test bench file is available for each core version that can be used to demonstrate and verify functional operation. Developers can use the provided Matlab utility to create a text file test vector stimulus and demonstrate the core receiving a time domain reference chirp input or a frequency domain chirp input.

For the latest pricing and availability information, please contact Mario Schiavone by phone at (201) 818-5900 ext. 229, or by email to

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