7/22/2003 - In an industry-first move to help designers meet the challenges of designing gigabit-speed PCB systems, Cadence Design Systems, Inc. (NYSE: CDN) announced the Cadence® 15.0 printed circuit board (PCB) and integrated circuit (IC) packaging design environment. The release, available now, includes enhancements and innovations spanning the entire integrated flow.
Now, for the first time, engineers have an integrated environment for designing and implementing gigabit serial interfaces in high speed PCB systems through a simulation and constraint-driven differential interconnect implementation from die-to-die across all three system fabrics: silicon, IC Package, and PCB. This robust capability puts first-time design success within the reach of computer and network companies.
Other advances that can enhance productivity include the following:
"The gigabit interconnect technology that allows systems designers to meet market demand for more system bandwidth is causing a revolution in design at the board and IC package levels," said Charlie Giorgetti, corporate vice president and general manager of the Cadence PCB Systems Division. "Engineers are facing unprecedented signal integrity, timing and routing issues, compelling them to look across design domains and consider the high-speed interconnect from I/O cell-to-I/O cell across IC packages and PCBs."
Designing the Gigabit Serial Interconnect
Key to successful gigabit serial interface design is the creation, constraint, simulation and management of differential signals throughout the entire design flow. Features in the Allegro® layout and SPECCTRAQuest® signal design and analysis environments enable designers and engineers to reduce design cycles by introducing the ability to design a comprehensive set of rules within a constraint management system and then use those rules to drive layout and routing. This can eliminate numerous iterations and enables first time design success.
Advanced Packaging Solution for Stacked-die Design and Analysis
As progressively more manufacturers turn to system-in-package (SiP) technology to reduce product footprint, integrate disparate technologies and reduce time to market, designing integral die stacks becomes increasingly attractive. A new multiple stacked-die design and editing environment and an automatic wirebond creation capability in the Cadence Advanced Package Designer can speed the design process, helping manufacturers get products to volume production quickly.
"SiP technology offers incredible performance and cost advantages for manufacturers. Designers, however, face enormous challenges in creating the requisite complex stacked-die structures," said Bret Zahn, vice president of Worldwide Design and Characterization, ChipPAC Inc. "As the market leader in stacked-die package design, assembly, and test, ChipPAC uses the new Cadence capability to deliver the highest-performance and most cost-effective packaging solutions to our customers."
Automating Library Part Creation, Validation and Management
New capabilities in PCB Librarian Expert 15.0 address process bottlenecks created as librarians manually struggle to enter, create and validate component data for the large pincount devices common in today's designs. The new release advances electrical component library development and management through the following:
Dynamic Real-time Copper Pour
Outer-layer ground planes are pervasive in today's complex, high-speed PCB designs, commonly used for shielding, noise reduction and supplying selective power to sensitive sub-circuits. Today, creating and modifying such entities can be very time-consuming due to complex manufacturability requirements. Addressing this in Allegro 15.0 is an improved solution for real-time copper pour that allows for dynamic plowing and healing during interactive or automatic routing. This helps cut design time by eliminating shape change-and-fix iterations. Importantly, the new feature allows shapes to be edited at any time - without any need for re-creation or post-processing, which can simplify the ECO process.
Model Integrity Environment
A new SPICE-to-IBIS Model Integrity module in the SPECCTRAQuest SI Expert solution helps users create IBIS models from SPICE models quickly. With the output of the SPICE simulation run, IBIS and Buffer options file, users can now create known good IBIS models quickly. Model Integrity identifies I-V and V-t tables for typical, maximum and minimum corner cases from the SPICE run file. Since the number of points in a SPICE simulation run could be far greater than the maximum number of points allowed in IBIS, Model Integrity SPICE-to-IBIS module applies an intelligent and proven best curve fitting algorithm to provide accurate IBIS models.
Cadence is the world's leader in electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,000 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.
Cadence, the Cadence logo, Allegro, Concept, Capture and SPECCTRA are registered trademarks and SPECCTRAQuest is a trademark of Cadence Design Systems, Inc.
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