Cypress Deals with Master Clock Failure with FailSafe Buffers

7/22/2003 - Cypress Semiconductor Corporation (NYSE: CY), a world leader in timing-technology solutions, announced availability of two FailSafeTM buffers (CY23FS04 and CY23FS08). FailSafe buffers provide an uninterruptible clock source for applications such as storage area networking or wireless basestations where continuous operation of the system is required to maintain mission-critical data in the event of a primary reference clock failure.

The unique FailSafe architecture allows for two user-selectable redundancy options: smooth switching to a secondary reference clock or maintaining the frequency of the failed primary reference clock as long as the power supply is operational. In addition, the devices add another layer of redundancy by providing continuous clock outputs even when both the primary and secondary reference clock fail.

FailSafe buffers rely on an internal digitally-controlled crystal oscillator (DCXO), which serves as the back-up clock source and drives the output signals. The DCXO maintains the last frequency and phase information from the reference clock prior to interruption; once the external clock source is restored, the DCXO automatically resynchronizes with minimal phase error. Because the outputs are driven primarily by the DCXO circuit, and only indirectly through the reference clock, FailSafe buffers completely eliminate the abrupt phase changes that typically occur when the user switches between two asynchronous reference clock sources.

“FailSafe buffers provide a simple and reliable method for clock redundancy and smooth switching in a variety of applications that handle mission-critical data,” said Tunç Cenger, marketing manager for Cypress's Timing Technology Division. “In addition, the CY23FS04 and CY23FS08, with their dynamically-controlled DCXO circuit, significantly reduce the jitter of the incoming reference clock. Finally, selectable frequency multiplication and division options complement the rich feature set to create the ultimate clock distribution device for systems with redundancy needs.”

FailSafe’s internal DCXO allows the user to define a tracking window or range for reference clock phase variations. This dynamic tuning range can be set to limit excessive input timing variations, such as jitter, as the signal is distributed in the system. The elimination of such variations leads to more accurate timing topologies, which are therefore capable of operating at higher frequencies.

The CY23FS04 is a 2.5 V or 3.3 V, 170 MHz zero-delay buffer with two reference clock inputs and four phase-aligned outputs. The CY23FS08 is a 2.5 V or 3.3 V, 200 MHz zero-delay buffer with two reference clock inputs and eight phase-aligned outputs, which can be configured to run at an integer multiple or factor of the reference frequency.

Pricing and Availability
The CY23FS04 is available now in a space-saving 16-pin TSSOP package. The CY23FS08 is available now in a 28-pin SSOP package. Prices range from $4.35 to $6.55 per unit in 25,000 unit quantities.

For more information on FailSafe products, visit the Cypress website at

About Cypress
Cypress Semiconductor Corporation (NYSE: CY) is Connecting From Last Mile to First MileTM with high-performance solutions for personal, network access, enterprise, metro switch, and core communications-system applications. Cypress ConnectsTM using wireless, wireline, digital, and optical transmission standards, including USB, Fibre Channel, SONET/SDH, Gigabit Ethernet, and DWDM. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers, and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions, and programmable microcontrollers. More information about Cypress is accessible online at

Previous Page | News by Category | News Search

If you found this page useful, bookmark and share it on: