Mentor, IBM to Develop, Qualify Design Files for Foundry Processes

7/2/2003 - Mentor Graphics Corporation (Nasdaq: MENT) announced that it has entered into an agreement with IBM to develop and qualify design technology files for IBM's CMOS, SiGe, RF CMOS and SOI processes. Mentor Graphics and IBM have provided Calibre design rule support for IBM foundry processes for several years. This formalized agreement expands the scope of support to deliver a complete, comprehensive set of physical verification rule files, parasitic extraction rule files and simulation models for IBM foundry processes. This support is intended to facilitate the rollout of IBM design kits providing fully integrated support for Mentor's tools throughout 2003.

Mentor Graphics will provide IBM with current and next-generation rule files for Calibre DRCTM, Calibre LVSTM (physical verification) and Calibre xRCTM (parasitic extraction), as well as EldoTM, Eldo RF and ADVance MSTM models for transistor-level simulation and mixed-language simulation. Mentor Graphics and IBM will work together to fully integrate these rule files and models into IBM's process design kits.

"IBM Design Kits that support tools from Mentor Graphics help drive the use of advanced manufacturing processes through accuracy, ease of use and data integrity," said Raminderpal Singh, senior engineering manager for IBM Microelectronics. "These tools are capable of handling advances in AMS SoC design and nanometer process technology, and meeting a wide range of customer requirements."

"This effort vastly expands IBM design kit support for Mentor's tools. It significantly reduces the barriers to AMS SoC development by providing the requisite rule files and models to expedite design creation," said Anthony Nicoli, director of marketing for Calibre at Mentor Graphics. "Mentor's innovative approach to verification, extraction and simulation lets designers rapidly analyze complex AMS SoC designs using accurate, mixed-level, post-layout data."

Calibre is the industry's only complete design-to-silicon tool suite. The Calibre physical verification tool suite, which includes Calibre DRC and Calibre LVS, ensures that IC physical designs conform to manufacturing rules and match the intended functionality of the chip. Calibre xRC is a robust, full-chip, parasitic extraction tool that delivers accurate, mixed-level parasitic data for comprehensive and accurate analysis and simulation. As the market leader in physical verification tools, Calibre is the industry standard, used in 19 of the world's 25 largest integrated device manufacturers, as well as all the top foundries and deep submicron library providers.

ADVance MS, Eldo and Eldo RF are part of Mentor's comprehensive solution for AMS and deep sub-micron designs. These simulation technologies allow circuit designers to verify the functionality and performance of very large and complex designs quickly and accurately while avoiding long verification cycles, excessive iterations and expensive silicon turns.

For a current list of supported processes please visit Inquiries regarding the availability of design kit files and models should be addressed to IBM.

About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site:

Mentor Graphics and Calibre are registered trademarks, and Calibre DRC, Calibre LVS, Calibre xRC, Eldo, Eldo RF and Advance MS are trademarks of Mentor Graphics Corporation.

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