7/1/2003 - Mentor Graphics Corporation (Nasdaq: MENT), the leader in FPGA design solutions, unveiled a new version of the FPGA Advantage® integrated design environment. FPGA Advantage 6.1 features a new design cockpit that integrates recent updates to the HDL Designer SeriesTM, ModelSim® and PrecisionTM RTL Synthesis products into the EDA industry's most interoperable and flexible design flow for managing FPGA design creation, verification and implementation.
"Mentor Graphics continues to execute on a strategy that provides individual designers and design teams with completely interoperable tool flows that manage the complexity of today's FPGAs," said Simon Bloch, general manager, FPGA Design Division, Mentor Graphics. "We were the first to integrate design creation, synthesis, and simulation and with FPGA Advantage 6.1 we look to extend data connections with more tools in the FPGA design flow."
Key to the design management features of FPGA Advantage is a new intuitive design cockpit that simplifies design creation and begins analysis the moment a design project is formed. Textual, tabular and graphical editors can be combined with design elements from ModuleWareTM, previous designs, external IP providers, and IP from FPGA vendors' macro and IP libraries. Combined, these elements provide a rich variety of design creation means to rapidly construct the FPGA. In addition, team design and analysis capabilities of the data provide easy navigation and the ability to search and organize data to aid in understanding design content.
"Complexity in FPGA design can be defined by the number of design files, the increasing number of system gates, higher performance characteristics or even the number and location of engineers on a design team," said Valerie Rachko, marketing director for HDL Designer Series and FPGA Advantage for Mentor Graphics. "FPGA Advantage offers a complete environment to manage the chaos of today's complex FPGA designs, while giving designers the freedom to achieve their design objectives."
Managing Verification from a Single Environment
FPGA Advantage provides several options for verifying a complex design. The tool accelerates the functional design development by focusing on optimizing the entire design creation, verification and modification design loop while providing the designer the flexibility to verify the way that matches his design style. Dynamic animation features enable the ability to view simulation results within the design creation editor to reveal high-level design and functional behavior, as well as enabling designers to debug a design exactly as it was entered.
Implementing a High-Complexity FPGA Design
FPGA Advantage features advanced synthesis capabilities to implement high-complexity FPGA designs. Integrating Precision RTL Synthesis, FPGA Advantage includes capabilities that transform FPGA vendor-independent hardware description language (HDL) code into a structural design that effectively leverages specific design architectures. With its vendor independent features, FPGA Advantage allows design teams to consider several component cost alternatives that can be leveraged to optimize product profit margins.
The synthesis engine in FPGA Advantage leverages a new Architecture Signature Extraction algorithm that provides data on how to best utilize the FPGA fabric as well as the available embedded memory, DSP block or clock management resources. The algorithm optimizes signal paths to achieve timing requirements that best leverage the features of the FPGA fabric.
Sharing the Design Results with Teams Downstream
Every design must be documented. FPGA Advantage automatically documents all stages of the flow using the Microsoft® Object Linking and Embedding (OLE) and HTML export formats. The documentation that is created is associated directly to the design, preparing for inevitable future design reuse.
Every FPGA must be placed on a printed circuit board (PCB). Integrating complex FPGAs on to a PCB may result in expensive PCB re-spins due to the introduction of manual data entry errors. Mentor Graphics is the only company with an integrated FPGA and PCB design flow that automates the physical chip and board integration process.
Pricing and Availability
FPGA Advantage 6.1 for Personal HDL Design is available now and includes HDL AuthorTM, ModelSim PE and LeonardoSpectrum Level 2 or Precision RTL and is available now starting at $15,000 for a node-locked license. The tool flow supports Windows® 2000, XP or NT 4.0.
FPGA Advantage 6.1 for HDL Design is available now and includes HDL Designer, ModelSim SE and Precision RTL and is available now starting at $53,600 for a floating license. The tool flow supports Windows® 2000, XP or NT 4.0; Sun Solaris 8, HP-UX 11.00 or 11.11; and Linux Red Hat 7.3.
For more information, please visit www.mentor.com/fpga-advantage.
About Mentor Graphics FPGA Solutions
Mentor Graphics is the market's single vendor source for an integrated solution for multi-million-gate field-programmable gate array (FPGA) design. The company's product portfolio includes best-in-class tools for design creation, simulation, synthesis, co-verification, embedded software, PCB and FPGA integration, and intellectual property. For more information, please visit www.mentor.com/fpga.
About Mentor Graphics Corporation
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.
Mentor Graphics, FPGA Advantage, ModelSim are registered trademarks of Mentor Graphics Corporation. HDL Designer Series and HDL Author are trademarks of Mentor Graphics.
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