Mentor Addresses Critical Design Creation with HDL Designer Series

7/1/2003 - Mentor Graphics Corporation (Nasdaq: MENT) announced the release of HDL Designer SeriesTM 2003.1, the latest version of the industry-leading environment for the creation, development and management of complex ASIC and FPGA semiconductor designs. HDL Designer Series 2003.1 includes new design management, creation, analysis and documentation capabilities. Mentor Graphics continues to enhance HDL Designer Series to be seamlessly interoperable with its best-in-class design flow, helping customers accelerate and simplify the development of leading-edge ASIC and FPGA designs.

"Complexity in all its dimensions, from the number of design files to the growing number of system gates, challenges traditional approaches to semiconductor design," said Valerie Rachko, marketing director, HDL Designer Series, Mentor Graphics. "With version 2003.1, we've added new design creation and management features that enable designers to navigate, organize and edit their designs in the format of their desire. We provide individuals with flexibility while providing organizations with the control to regulate how designs are shared through companies or across generations."

A Predictable, Flexible Design Process Minimizes Design Risk
Today's multi-million gate semiconductors require a team design approach and rigorous data and process management. At the heart of the enhancements to HDL Designer Series is the Design ManagerTM tool. The Design Manager tool provides easy design navigation and the ability to search and organize data to aid in understanding design content and relationship of design data files and objects. Designers can sort, group and filter data based on any design unit attribute and instantly view any portion of the design hierarchy. In addition, HDL Designer Series now includes a shortcut bar with quick access to common functions such as: Project, Explore, Tasks and Viewpoints.

Rapid Design Development Improvements Increase Productivity
New to HDL Designer Series is DesignPad, a design-aware, fully customizable hardware description language (HDL) code editor. DesignPad allows users to access design data through a code browser that allows them to rapidly navigate HDL code. DesignPad provides immediate access to any code files, blocks, and constructs, enabling comparison, error cross-referencing, graphical representation of all dimensions of text entry.

Additional entry methods Include Interface-Based DesignTM (IBDTM), a unique tabular design methodology for rapidly editing structural HDL for large and complex designs, and ModuleWareTM, which generates silicon-vendor-independent logic for a variety of common logic functions. HDL Designer Series 2003.1 also includes intuitive graphical editors, such as block diagrams, state machines, flow charts and truth tables.

Practical IP and Design Reuse
Design reuse is a reality in all facets of semiconductor design. Through IBD, block diagrams and the ability to view the design hierarchy, HDL Designer Series 2003.1 allows the user to visualize virtually every aspect of the design, rapidly advancing design comprehension. The DesignPad can look deeper inside the design units to navigate ports and declarations, and generate graphical views of the text.

Powerful and Early Design Analysis Cuts Verification Time
With as much as 80 percent of design time spent in verification, methods to speed this integral process will greatly impact designers meeting today's strict time-to-market demands. HDL Designer Series 2003.1 works with HDL simulators including ModelSim® to enhance their design analysis capabilities. Graphical and tabular design views in HDL Designer Series interact live during simulation.

Automated Communications for Distributed Design Teams
Designs today are more difficult to communicate and bigger designs require more design reviews. More and more often design groups are now distributed, either geographically or across company boundaries. HTML export documentation in HDL Designer Series 2003.1 enables global design teams to securely share and publish designs for design reviews and later reuse. Designers can share information with customers and partners, while controlling how much data is visible to shield proprietary or incomplete code.

Pricing and Availability
HDL Designer Series 2003.1 is available now and starts at $2,000 US for a node-locked license. The tool suite is now available for Windows® XP, Red Hat Linux 7.3, Solaris 9 and HP-UX 11.11 platforms in addition to existing support for Windows NT and 2000, Solaris 7 and 8, HP-UX 11.00, and Linux Red Hat 7.2. For more information, please visit

HDL Designer Series 2003.1 is included in FPGA Advantage 6.1, also announced today. FPGA Advantage is the EDA industry's most interoperable and flexible design flow for managing FPGA design creation, verification and implementation. For more information, please visit

About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site:

Mentor Graphics and ModelSim are registered trademarks of Mentor Graphics Corporation. HDL Designer Series, HDL Pilot, HDL Detective, HDL Author, HDL Designer and Debug Detective are trademarks of Mentor Graphics.

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