6/3/2003 - Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) design software, announced that the GalaxyTM Design Platform and other Synopsys tools have been integrated into TSMC's advanced Reference Flow 4.0. The TSMC Reference Flow version 4.0 targets designs implemented in TSMC's 130-nanometer (nm) and Nexsys 90-nm process technologies, and addresses design issues such as signal integrity (SI) closure, multi-threshold voltages and design for manufacturability (DFM) rules. Reference Flow 4.0 is the result of a long-standing collaboration between TSMC and Synopsys in developing proven flows that provide mutual customers with higher productivity and better design quality.
"TSMC and Synopsys have been working together since the release of the TSMC Reference Flow 1.0 about three years ago," said Genda Hu, vice president of Corporate Marketing at TSMC. "This latest collaboration has produced a comprehensive offering that uses Synopsys' RTL to GDSII tools to solve complex 90-nanometer design issues and tradeoffs between speed and leakage power. The result is a proven method that manages nanometer-scale design risks and delivers faster time to volume when used in conjunction with TSMC's advanced process technologies."
Comprehensive Signal Integrity Solution
The TSMC Reference Flow provides powerful timing and SI closure using physical synthesis and physical optimization technology within Galaxy SI. Galaxy SI is a complete signal integrity solution within the Galaxy Design Platform that addresses crosstalk delay, noise (glitch), IR (voltage) drop and electromigration. Galaxy SI provides designers with a more comprehensive SI solution that includes prevention, analysis, and repair, speeding SI closure for 130-nanometer designs and below.
"By working together, Synopsys and TSMC have provided an environment where customers can be assured of a smoother path to tape out for aggressive, complex designs," said Paul Platt, vice president of design services at IDT, a leading communications IC company. "IDT is a long-time customer of both companies and recently used Synopsys' AstroTM and HerculesTM to successfully tape out a 90-nanometer test chip using TSMC's advanced silicon process. With Synopsys' and TSMC's collaboration, we were able to design a complex, silicon device for TSMC's process."
Design for Manufacturing (DFM) Rules and Multi-threshold Voltages
The Reference Flow 4.0 provides a solution for addressing DFM rules for the 90 nanometer process, including process variation modeling, metal over via/contact enclosure, redundant via insertion, dummy OD/Poly/Metal insertion and modeling of shallow trench isolation (STI), and length of diffusion (LOD) effects - all of which are becoming critical to improving wafer yield. Synopsys' Astro provides support for 90 nanometer design rules to address the critical DFM requirements. Hercules, Star-RCXTTM, and HSPICE® handle the RC extraction, LVS and simulation of STI LOD effects. The Reference Flow 4.0 also addresses leakage power optimization, based on multi-Vt core cell libraries using Synopsys' Design Compiler®, Power CompilerTM, and Physical Compiler® tools.
"TSMC's leading process technologies have been driving the most advanced flow requirements. Synopsys and TSMC's ongoing collaboration has resulted in silicon-proven methodologies that help manage the most critical design risks for complex systems on chip," said Rich Goldman, vice president of Strategic Market Development at Synopsys, Inc. "Our leading-edge customers look to us to jointly develop future flows and to proactively anticipate and solve new design implementation challenges that enable faster time to tape out for our customers."
The TSMC 4.0 reference flow is available immediately. The TSMC 4.0 reference flow provides a complete RTL-to-GDSII solution and includes Synopsys' Design Compiler, Physical Compiler, Astro, Astro-RailTM, Astro-XtalkTM , Floorplan Compiler, DFT Compiler, TetraMAX®, VCSTM, Power Compiler, Star-RCXT, PrimeTime®, PrimeTime SI, Hercules and HSPICE.
Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
Synopsys, Design Compiler, HSPICE, Physical Compiler, PrimeTime and TetraMAX are registered trademarks of Synopsys, Inc. Astro, Astro-Rail, Astro-Xtalk, Galaxy, Power Compiler, Star-RCXT, VCS and Hercules are trademarks of Synopsys.
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