Synopsys Addresses Crosstalk Delay with Galaxy Enhancements

6/3/2003 - Synopsys, Inc. (Nasdaq: SNPS), the world leader in integrated circuit (IC) design software, announced GalaxyTM SI, a new and complete signal integrity (SI) solution within the Galaxy Design Platform that addresses crosstalk delay, noise (glitch), IR (voltage) drop and electromigration. Galaxy SI provides designers with comprehensive prevention, analysis and sign-off, speeding SI closure for 130-nanometer designs and below.

"We used Galaxy SI in our UNICAD design environment for signal integrity prevention and sign-off of our 120-nanometer production designs, and have now adopted the solution for our next-generation 90-nanometer designs," said Jean-Pierre Geronimi, director of Computer Aided Design, STMicroelectronics Research and Development. "Synopsys' Galaxy SI offers the most complete signal integrity solution available for designers today, integrates readily into our flow, and speeds timing and SI closure."

Existing SI solutions are incomplete in that they offer a mix of point tools or they rely on third-party sign-off, which can result in delayed SI closure, or even worse, silicon failure. In contrast, Synopsys' Galaxy SI solution provides an integrated platform with comprehensive SI support at all stages of the design flow, from implementation to sign-off. Galaxy SI uses PrimeTime®'s golden delay calculator and common design infrastructure - common libraries, constraints, and database - to ensure consistent timing and SI analysis throughout the design flow. This enables designers to progressively eliminate problems as they move from design planning to placement to routing and sign-off, resulting in faster SI closure.

Galaxy SI is easy to adopt because it is built into the Galaxy Design Platform. All of Galaxy SI's capabilities are integrated into proven tools, within the platform, which are already the foundation of many customers' design environments. Customers can tape-out with confidence, because sign-off in Galaxy SI is based on PrimeTime, the industry's most pervasive full-chip static timing sign-off solution.

"The challenges presented by designs at 130 nanometers and below demanded a new solution and approach to ensure timing and SI convergence," said Don Friedberg, director of Design Methodologies at Agere Systems. "Using Synopsys' AstroTM, part of the new Galaxy SI solution to prevent and repair crosstalk-induced problems during place and route, we have achieved first-pass SI success on our multimillion-gate 130 nanometer designs."

"TSMC first qualified Synopsys' signal integrity tool suite to enhance the process-specific design methodology for our 130 nanometer and Nexsys 90 nanometer process technologies last October," said Ed Chen, director of Design and e-Service Marketing at TSMC. "The highly-integrated signal integrity prevention and analysis capability has been included in TSMC Reference Flow Release 4.0 which is announced today. We expect our customers who take advantage of this capability to achieve rapid timing and SI closure of their SoC designs."

"To overcome the challenges we faced with our earlier chips, we were looking for an SI solution that complemented our current tool investment," said Henrik Pallisgaard, director of Product Development, Ethernet Products Group, Vitesse Semiconductor Corporation. "Synopsys' Galaxy SI solution provided us with a comprehensive set of capabilities to analyze and prevent crosstalk throughout our flow. On a recent design, we were able to achieve chip-level timing in less than four weeks. We have already achieved first-pass silicon success with Galaxy SI and, as a result, have adopted it into our flow."

"Synopsys continues to enhance the Galaxy Design Platform to address our customers' critical design challenges," said Sanjiv Kaul, senior vice president, Corporate Applications and Marketing, Synopsys, Inc. "The adoption of Galaxy SI demonstrates the comprehensiveness of the SI solution we offer, and our customers' confidence in the platform."

About Galaxy Design Platform
The Galaxy Design Platform is an open, integrated design implementation platform with best-in-class tools, enabling advanced IC design. Anchored by Synopsys' industry-leading IC implementation tools and the open MilkywayTM database, the Galaxy Design Platform incorporates consistent timing, SI analysis, common libraries, delay calculation, and constraints from RTL all the way to silicon. The Galaxy Design Platform helps reduce design time, decreases integration costs and minimizes the risks inherent in advanced, complex IC design.

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at

Synopsys and PrimeTime are registered trademarks of Synopsys, Inc., and Astro, Galaxy and Milkyway are trademarks of Synopsys, Inc.

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