Cadence Leads with Vision at DAC
5/29/2003 - Cadence Design Systems, Inc. (NYSE:CDN) will lead the upcoming Design Automation Conference (DAC) with an impressive line-up of over 20 presentations. At DAC, June 2 through 6, in Anaheim, Calif., Cadence will also showcase the technologies assisting customers around the world navigate today's toughest design-to-volume challenges. Specific opportunities to hear the Cadence vision for the future and attend demonstrations of Cadence technology include:
Cadence-Sponsored Lunch Panel: Outsourcing Design: A Good Thing Or A Bad Thing?
Anaheim Convention Center, Room 207 A&B
Monday, June 2
10:00 a.m. to 2:00 p.m.
Moderator: Mike Santarini of EE Times
Panelists: Gary Smith of Gartner/Dataquest; Glenn Dukes of Synopsys;
Paul Estrada of Cadence; Karla Reynolds of IBM Foundry Operations;
Ronnie Vasishta of LSI Logic; and, Mike Gianfagna of eSilicon.
Cadence Keynote Speaker: Penny Herscher, Executive VP and Chief Marketing Officer of Cadence
Workshop for Women in EDA
Anaheim Convention Center, Room 205AB
Monday, June 2
2:00 p.m.
DAC Pavilion Panel: Ask the CTO
Speaker: Ted Vucurevich, CTO of Cadence
Anaheim Convention Center, Booth 1372
Monday, June 2
1:00-2:00 p.m.
PSL/Sugar Consortium
Speaker: Stan Krolikoski, Vice President of Cadence's
Functional-Verification Group
Anaheim Convention Center, Room 202 A&B
Tuesday, June 3
9:00 a.m.
Panel: COT - Customer Owned Trouble?
Speaker: Aurangzeb Khan, Vice President and General Manager of Cadence Silicon Engineering Group
Anaheim Convention Center, Room 207A-D
Tuesday, June 3
2:00-4:00 p.m.
Artisan/Cadence Breakfast Event: Enabling SoC Success for 130-Nanometers and Below
Speaker: Jim McCanny, Technical Marketing Director at Cadence
Anaheim Convention Center, Room 304 A
Wednesday, June 4
7:30-9:00 a.m.
Panel: Mixed Signals on Mixed Signal: The Right Next Technology
Speaker: Kurt Johnson, Services Group Director at Cadence
Anaheim Convention Center, Room 207A-D
Wednesday, June 4
8:30-10:00 a.m.
System-Level Symposium
Anaheim Convention Center, Room 303 AB
Wednesday, June 4
12:00-2:00 p.m.
Moderator: Richard Goering of EE Times
Panelists: Gary Smith of Gartner/Dataquest; Serge Leef of Mentor Graphics; and, Stan Krolikoski of Cadence
DAC Pavilion Panel: Platforms-YES, But What Type is Best?
Speaker: Grant Martin, Cadence Fellow and Chief Technologist for the Front End Products/System Level Design and Verification Group
Anaheim Convention Center, Booth 1460
Wednesday, June 4
1:30-2:30 p.m.
Panel: Nanometer Design: Place Your Bets
Anaheim Convention Center, Room 207A-D
Wednesday, June 4
4:30-6:30 p.m.
Panelists: Louis Scheffer of Cadence; Shekhar Borkar of Intel; John Cohn of IBM; Antun Domic of Synopsys; Patrick Groeneveld of Magma Design Automation; and, Jean Pierre Schoellkopf of STMicroelectronics.
Cadence Berkeley Labs Keynote Speaker: Alberto L. Sangiovanni-Vincentelli, Chief Technology Advisor
The Tides of EDA
Anaheim Convention Center, Ballroom A-C
Thursday, June 5
1:00-1:45 p.m.
For additional information about Cadence at DAC visit dac.cadence.com.
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