5/22/2003 - Virage Logic (Nasdaq:VIRL), a leading provider of best-in-class semiconductor IP platforms, will demonstrate the key benefits of its newly announced Technology-Optimized Platforms at this year’s Design Automation Conference (DAC), June 2–6 in Anaheim, California. In addition, the DAC conference program will include presentations by Virage Logic executives on IP business model and System-on-Chip (SoC) test issues.
Virage Logic’s Technology-Optimized Platforms aim to meet the critical requirements of reducing silicon costs and failure risks, while boosting performance and ensuring high manufacturing yields for a particular foundry or Integrated Device Manufacturer (IDM) process. By providing silicon-proven, integrated IP that is compatible with all the major EDA flows, Virage Logic’s Technology-Optimized Platforms address the needs of complex and mainstream SoC designs.
The new Technology Optimized platforms will be featured at the Virage Logic booth (#1735) and suites (#2602). In addition, Virage Logic will showcase some of its foundry, EDA and IP partners in jointly delivered overview presentations in its suites. For detailed information about the various presentations and to register, visit http://www.viragelogic.com.
In addition, Virage Logic engineering director Mike Colwell will be a co-presenter of “SoC Design Solutions Using Virage Logic & Synopsys Galaxy” at Synopsys suite (#2614) at 9:00am on Monday, June 2. Visit http://www.synopsys.com/links/dac_reg.html to register.
Executives to Share Key Insights on IP Business Models and SoC Test Issues
Raj Singh, vice president of worldwide sales for Virage Logic, will participate in an FSA Management Forum Day panel session entitled “IP Business Models.” This session will help attendees learn to navigate through a host of business models, licensing issues and technical hurdles. They will also learn how to shorten the time it takes to use third-party IP. Visit http://www.fsa.org/events/event.asp?event=2003/dac0603 to register.
On Thursday, June 5, Virage Logic’s vice president and chief scientist Yervant Zorian will lead a conference session entitled “Novel Approaches in Test Cost Reduction.” Dr. Zorian will also conduct an all-day “SoC Test Strategies” tutorial on Friday, June 6. Visit http://www.dac.com to register.
About Technology-Optimized Semiconductor IP Platforms
Virage Logic’s Technology-Optimized Platforms are based on its highly differentiated IP including the Self-Test and Repair (STAR) Memory System, the Area, Speed and Power (ASAP) MemoryTM product line, the ASAP LogicTM product line with its metal programmable and standard cell libraries, and the recently introduced Base I/O libraries. Technology-Optimized Platforms enable customers to expedite the creation of next generation products by addressing the increasingly complex task of identifying and obtaining the semiconductor IP needed to produce successful, on-time products. Virage Logic’s semiconductor IP platform strategy calls for the delivery of Technology-Optimized Platforms for a broad range of third-party foundry and IDM processes.
About Virage Logic
Virage Logic Corp. (Nasdaq:VIRL) is a leading provider of best-in-class semiconductor IP platforms based on memory, logic, I/Os, and IP development tools that are silicon-proven and production ready. Virage Logic meets market demands for cost reduction, while improving performance and reliability for fabless and integrated device manufacturer (IDM) companies focused on the consumer, communications and networking, handheld and portable, and graphics markets. Virage Logic is headquartered in Fremont, California and has sales and support offices worldwide. For more information, visit www.viragelogic.com or call (877) 360-6690 toll free or (510) 360-8000.
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