Sequence, Toshiba Plug Power Leaks with Selective Multi-Threshold CMOS

5/22/2003 - Sequence Design announced a joint development effort with Toshiba Corporation to optimize power and reduce wasted power consumption in semiconductors. This methodology is based on Toshiba’s Selective MTCMOS (Multi-Threshold CMOS) technology.

The problem of leakage currents is growing at an exponential rate at line widths below 90 nanometers, according to Takashi Yoshimori, System LSI Division technical executive, Toshiba Semiconductor.

"It is now common for 20 percent or more of a chip's power budget to be consumed by leakage power alone, severely limiting the designer's ability to maximize circuit efficiency and performance," Mr. Yoshimori said. "Sequence's leakage power methodology provides us with a way to turn the power supply to logic on and off as needed, eliminating waste and greatly extending battery life for handheld products."

"We are honored to have the opportunity to partner with Toshiba to address the industry's growing concern about low power design. As Dr. Gordon Moore noted at this year's ISSCC conference, leakage power is a trend that is spiraling out of control." said Vic Kulkarni, Sequence president and CEO. "By working in concert with the most advanced design and process-science talent, we can be assured that our joint breakthrough on leakage power will be well suited to the challenge of power consumption at the nanometer level."

The Leakage Problem
Leakage control has become a major design issue due to leakage currents that drain a battery's charge even when a wireless device is inactive or in standby mode. Transistors in each new process generation are leakier than those in previous generations (due to transistor scaling effects), only exacerbating the problem.

Leakage is also an issue in active mode, when the transistors are operational, as any power wasted due to leakage is not available to be allocated to performance enhancing logic - that is, leakage power comes right off the top of the overall power budgets.

Sealing the Leak
The Sequence power methodology includes fully automatic gate level power optimization technology for the reduction of both dynamic and leakage power. The optimizations may be run independently or together with no adverse impact on area or timing.

Sequence's power optimization tools reduce both active and standby leakage currents. Active mode leakage is reduced through the use of two optimization features: Dual-threshold (dual-Vt) substitution and Resizing. Both features work by trading off positive slack timing for reduced leakage. The Dual-Vt optimization substitutes High-Vt cells (which are slower but leak much less) along fast paths. Resizing optimization reduces transistor size along fast paths and results in reduced leakage since smaller transistors leak less. Resizing also reduces dynamic power.

Sequence, in partnership with Toshiba, is adding to its power optimization suite by developing an MTCMOS optimization tool. MTCMOS, sometimes referred to as power-gating, works to reduce leakage currents by disconnecting the power supply from portions of the circuit when those portions are inactive. Leaking currents are prevented by inserting a series switch transistor between the logic cells and the power supply or ground. The switch is closed when the logic is operational and opened when the logic is inactive. Reductions of 10x to 100x in leakage can be achieved.

Sequence's MTCMOS approach utilizes patent pending optimization algorithms that result in minimum area overhead and no performance degradation. All physical design issues are automatically resolved while concurrent electrical checks ensure that the logic and signaling do not violate user-specified limits on key electrical parameters such as virtual ground voltages and currents.

"Leakage current is the big stumbling block to Moore's Law, and MTCMOS Power-gating is one of the most effective ways to reduce leakage currents and overall power consumption," explained Professor Takayasu Sakurai of the University of Tokyo. "Power-gating optimization, however, has until now not been fully realized in a practical design environment. Thus, this joint development by Toshiba and Sequence Design will be of great value to both VLSI designers and VLSI customers. Additionally, the collaboration between the circuit design team and the EDA team is very significant since the solution to recent deep submicron issues requires both circuit knowledge and EDA expertise."

Leverages NanoCool Experience
The addition of MTCMOS technology to Sequence's PhysicalStudio leverages the company's experience in low-power design tools as part of its NanoCool Initiative, a joint venture between semiconductor designers, EDA tool vendors, IP companies, and library suppliers, to provide a complete flow offering concurrent power management, timing and signal integrity capabilities to achieve rapid design closure at 90 nanometers and below.

PhysicalStudio optimizes chip timing and signal-integrity issues concurrently, both before and after routing. It is fully interoperable with industry-standard routing tools, permitting existing physical design flows to reach fast, predictable design closure.

PhysicalStudio allows system-on-chip designers to:

By unifying placement-driven optimization and post-route optimization into a single engine, the product ensures that every net in a design is correctly driven and all timing and signal integrity violations are eliminated. PhysicalStudio operates on large, hierarchical designs with varying abstractions at the top-level such as register-bounded blocks, STAMP, and LIB.

About Toshiba
Toshiba Corporation is a leader in information and communications systems, electronic components, consumer products, and power systems. The company's integration of these wide-ranging capabilities assures its position as a leading company in semiconductors, displays and other electronic devices.

Toshiba has 176,000 employees worldwide and annual sales of over US $40 billion. Visit Toshiba's website at

About Sequence
Sequence Design, Inc. enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence's power and signal integrity software give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of nanometer design.

Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 50 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections and Mentor Graphics' Open Door partnership programs. Additional information is available at

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