5/20/2003 - Mentor Graphics Corporation (Nasdaq: MENT) announced a comprehensive FPGA design flow that expands traditional FPGA tools with new technologies to address emerging challenges of complex FPGA designs. The three-part flow, which extends from high-level FPGA design through Printed Circuit Board (PCB) design, includes existing and future technologies for the design and verification of the FPGAs, embedded systems, and PCBs containing FPGAs.
The combination of large, complex IP blocks, memories, high speed IO, hard and soft embedded processors and embedded software on a single FPGA, exacerbated by the soaring system gate counts and packaging requirements, taxes the capabilities of traditional design methodologies. The design of these chips requires a new degree of sophistication, characterized by deeper, system-level design, concurrent hardware/software design and verification at all stages of the design process. To avoid a design gap in FPGA solutions, Mentor continues to execute on a strategy to provide integrated tools that continue to address the complexity of new architectures, thereby helping designers preserve the inherent productivity advantages of FPGAs.
"Mentor Graphics is the only EDA company with a fully integrated tool solution capable of handling all aspects of FPGA design, from verification and synthesis to embedded software and board layout," said Walden C. Rhines, chairman and CEO of Mentor Graphics. "We are advancing our position in FPGA design by building beachheads around our tools that are de facto standards in their respective markets."
"The device complexity of FPGAs continues to increase rapidly with the advent of new architectures," said Simon Bloch, general manager of the FPGA Design Division. "To maintain the design productivity advantage of FPGAs and complement the traditional FPGA design flows, customers are shifting to design approaches that mirror those of ASICs. Mentor Graphics offers the most complete portfolio of products to address the increasing challenges of FPGA designers."
The Mentor Graphics® FPGA Design Tool Flow
Mentor Graphics is continuing its commitment to provide a comprehensive, fully integrated suite of design tools tailored for the next generation of programmable logic device architectures. Mentor Graphics will continue to deliver new tools and enhancements to existing tools that address the following areas:
FPGA Design and Verification
The Mentor Graphics design creation and implementation flow includes tools for design entry and management, synthesis and simulation and a library of intellectual property (IP) cores to aid design reuse methodologies.
Design Creation and Management
Responding to the trend in increasing FPGA device size and complexity, Mentor Graphics offers the HDL Designer SeriesTM product, its industry-leading design creation and management tool. The tool suite delivers the performance and capacity necessary to design FPGAs beyond 50 million system gates. The HDL Designer Series product is a flexible environment to manage these complex designs, and contains various text, tabular and graphical design editors to aid in creating the FPGA. The tool suite offers visually enhanced debugging and analysis with the ModelSim® tool and provides practical ways to comprehend IP and code reuse, a necessary part of any complex design. It also supports both HTML and OLE communication methods that are essential for design documentation. General availability of the next release of the HDL Designer Series product is scheduled for Q2 2003.
The Mentor Graphics PrecisionTM RTL synthesis product is now available for general distribution to new and existing LeonardoSpectrumTM customers. The tool provides a new intuitive use model, superior quality of results and advanced incremental design analysis capabilities. Qualifying customers of Mentor's previous generation synthesis tool, LeonardoSpectrum, have the option to upgrade to the Precision RTL Synthesis tool at no cost. In addition, the Precision RTL Synthesis tool will become the synthesis engine for the latest version of the FPGA Advantage® environment, the company's industry-leading flow for design creation, simulation and synthesis.
"When using Precision RTL Synthesis tool, a simple synthesis run offers convincing area and timing estimates so that the number of place-and-route runs can be reduced considerably," said Johann Notbauer, technical director, CES Design Services, a business unit of Siemens Program and System Engineering. "Because each place-and-route run can take twelve hours or more for a complex design, this saves valuable time and yields better results."
Mentor Graphics continues to expand the Precision Synthesis tool solution to help designers accelerate the lengthy timing closure process by minimizing place-and-route iterations. The physical synthesis technologies provide automated physically aware algorithms that use placement and post-place-and-route timing information for retiming, replication and re-synthesis. This can eliminate lengthy design iterations, multiple place-and-route iterations and floorplanning steps. After automation has done as much as possible, the tool offers designers an interactive environment for manual improvements to further tune designs to achieve faster performance or desired speed grades. General availability of the physical synthesis technology is expected in the second half of 2003.
To accommodate the need to design large and complex FPGAs efficiently, the Precision product line is incorporating technologies to raise the level of design abstraction from RTL to C. These new technologies enable designers to quickly trade-off design performance and area by working at the algorithmic level of the design, allowing for rapid exploration and implementation. General availability of the high-level synthesis technology is expected at the end of 2003.
The Mentor Graphics flagship verification product is its market-leading HDL simulation tool, ModelSim. The ModelSim product includes many features that accelerate FPGA verification and is the de facto industry-standard solution for the FPGA market. The top five FPGA vendors currently distribute vendor-specific versions of the ModelSim environment. Mentor Graphics continues to work with all key FPGA vendors to ensure that the ModelSim product meets or exceeds end-user performance requirements. The product will continue to be enhanced in the upcoming months with more powerful debug capabilities, expanded code coverage and increased performance.
An Integrated FPGA Design Solution
Mentor Graphics was the first company to bring to market an integrated flow for design creation, management, simulation and synthesis with its FPGA Advantage product. The FPGA Advantage tool empowers FPGA designers with a faster path from concept to implementation. The new version of the FPGA Advantage tool, slated for release in Q2 2003, will include the latest versions of the HDL Designer Series product for design creation and management, the Precision Synthesis tool for synthesis and timing analysis and the ModelSim tool for simulation.
Mentor Graphics is exploring the application of formal verification techniques in an FPGA design flow. Formal verification is recognized in the ASIC market as a critical method for proving that two designs are functionally identical. As FPGA designs continue to mirror ASICs in complexity, Mentor Graphics recognizes the potential opportunities for formal verification within an FPGA design flow.
Design reuse becomes paramount as device sizes begin to rival those of ASICs. Mentor continues to expand its relationships with the FPGA vendor community to provide access to intellectual property from its InventraTM portfolio. Today, Mentor has key relationships with leading FPGA vendors to provide platform-targeted IP libraries. These relationships will be extended with further announcements expected starting at the end of 2003.
Embedded Software Integration and Development
When hard or soft microprocessors are included on a programmable platform, designers face the additional challenges associated with embedded software development. Embedded software design requirements include software development tools, integrated development environments (IDEs), hardware-connection probe tools and real-time operating systems (RTOS) and associated middleware that specifically support both hard and soft processor core technologies.
To support these trends, Mentor offers a complete software development suite that includes cross compilers and debuggers in an embedded IDE, closely linked to the NucleusTM RTOS, TCP/IP networking stack and other middleware that has been ported to many of the popular processors used in programmable devices. Both development tools and RTOS have been validated with devices from Altera and Xilinx, including recently announced comprehensive support for Altera's NIOS-based devices. Further announcements on the Nucleus RTOS design kits for FPGA devices will be made throughout 2003.
As the design focus shifts from content creation to the challenges of evaluating, integrating and verifying multiple pre-existing blocks and software components, designers will deploy advanced verification tools such as co-verification. Virtual prototyping with the Mentor Graphics Seamless® Co-Verification Environment (CVE) allows designers to visualize system operation of the FPGA weeks or months ahead of the time when the first physical prototypes can be programmed. Mentor Graphics has partnered with Altera, Xilinx, and Atmel to tailor co-verification solutions for designers embedding the cores onto FPGA devices. Moving forward, Mentor will continue to support a broader range of devices as they become prevalent in the market.
Design creation and verification tools such as the Mentor Graphics Platform ExpressTM Design Environment can guide users through complex embedded system development, facilitating the attachment of microprocessor cores, blocks of logic, and software modules into platform designs. But with modern programmable logic devices, there is a potentially huge divide between what can be put in the chip versus what can be verified to work. Bridging this gap requires the integration of many pieces of the hardware/software design and verification paradigm: software debugging, event-driven logic simulation and complex IP modeling in a variety of verification environments. The Mentor Graphics Platform Express tool will enable the development of complex FPGAs with embedded cores. Availability of an FPGA-specific version of the Platform Express tool is expected in the second half of 2003.
PCB System Design and Verification
Traditionally, FPGA design and PCB design is done separately by distinct design teams using different EDA tools and processes. The existence of multiple design processes creates inter-process connectivity and timing closure problems, which negatively impact both performance and cost-to-market for designers. FPGA pin counts can exceed 1500 pins causing time-consuming PCB symbol generation and management tasks. During speed optimization or logic changes, FPGA pin assignment modifications often require time-consuming manual schematic updates and PCB re-routing.
Mentor's FPGA BoardLinkTM product automates the critical time-consuming and error-prone tasks faced by the PCB designer. Schematic symbol generation is automatic, utilizing implementation- specific FPGA signal names from the FPGA Advantage tool, while leveraging corporate PCB library information. The user is given the added option of user-directed symbol fracturing allowing high pin count devices to be broken down into multiple symbols. FPGA pin assignments change typically three times or more during a design phase. The FPGA BoardLink product incorporates these pin assignment changes from the FPGA Advantage design environment with automatic updates to the schematic symbol removing the need to re-wire the PCB schematic. First customer availability is expected in June of 2003.
FPGA designs continue to push the high-speed performance envelope with multi-gigabit I/O capability. This capability demands tight integration of timing and signal integrity analysis within the PCB design flow. Mentor Graphics has partnered with Xilinx, Altera and Actel to provide a combination of new analysis capabilities and certified high-speed design kits that FPGA designers need to meet their multi-gigabit design requirements. Mentor Graphics also leads modeling format standardization efforts to support multi-gigabit design requirements. The company is also working with FPGA vendors to implement these standards, ensuring model availability and implementation is seamless for all customers. These modeling extensions dramatically increase the simulation capability and accuracy provided in Mentor's tools, while at the same time reducing the modeling effort for end users. Finally, high-speed design principles and methods represent a new frontier for many FPGA designers. To help solve these new challenges, Mentor is working with the FPGA vendors and supplying signal integrity tools to enable field application engineers to educate their teams on the topics of high-speed design.
For pricing on any of the Mentor Graphics FPGA design tools, please call 1.800.547.3000 or visit www.mentor.com/fpga.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.
Mentor Graphics, ModelSim, Seamless, FPGA Advantage and Nucleus are registered trademarks and Precision Synthesis, LeonardoSpectrum, HDL Designer Series, Inventra, Platform Express, and FPGA BoardLink are trademarks of Mentor Graphics Corporation.
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